Distributed Quantum Error Correction for Chip-Level Catastrophic Errors

Qian Xu, Alireza Seif, Haoxiong Yan, Nam Mannucci, Bernard Ousmane Sane, Rodney Van Meter, Andrew N. Cleland, and Liang Jiang

Phys. Rev. Lett. 129, 240502 – Published 6 December 2022

Abstract

Quantum error correction holds the key to scaling up quantum computers. Cosmic ray events severely impact the operation of a quantum computer by causing chip-level catastrophic errors, essentially erasing the information encoded in a chip. Here, we present a distributed error correction scheme to combat the devastating effect of such events by introducing an additional layer of quantum erasure error correcting code across separate chips. We show that our scheme is fault tolerant against chip-level catastrophic errors and discuss its experimental implementation using superconducting qubits with microwave links. Our analysis shows that in state-of-the-art experiments, it is possible to suppress the rate of these errors from 1 per 10 s to less than 1 per month.

Received 11 April 2022
Accepted 6 October 2022

DOI:https://doi.org/10.1103/PhysRevLett.129.240502

Physics Subject Headings (PhySH)

Quantum error correction Quantum information architectures & platforms Quantum information processing Quantum networks

Superconducting qubits

Quantum Information, Science & Technology

Authors & Affiliations

Qian Xu ^1,*, Alireza Seif ^1,*, Haoxiong Yan ¹, Nam Mannucci¹, Bernard Ousmane Sane ², Rodney Van Meter ³, Andrew N. Cleland ^1,4, and Liang Jiang ^1,†

¹Pritzker School of Molecular Engineering, The University of Chicago, Chicago, Illinois 60637, USA
²Graduate School of Media and Governance, Keio University, 5322 Endo, Fujisawa 252-0882, Japan
³Faculty of Environment and Information Studies, Keio University, 5322 Endo, Fujisawa 252-0882, Japan
⁴Center for Molecular Engineering and Material Science Division, Argonne National Laboratory, Lemont, Illinois 60439, USA

^*These authors contributed equally to this work.
^†liang.jiang@uchicago.edu

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Vol. 129, Iss. 24 — 9 December 2022

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Figure 1
(a) Information is encoded in an error correcting code that is distributed across multiple data chips. The CRE-induced erasure errors on the data chips are corrected using ancilla-assisted syndrome measurements. (b) A code that corrects $d - 1$ erasure errors, suppresses the rate of the CRE-induced catastrophic events.
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Figure 2
(a) The illustration of the $[[4, 1, 2]]$ (left) and the $[[7, 1, 3]]$ (right) code. The colored plaquettes represent stabilizer generators that have supports on the surrounding vertices (data qubits). (b) The FT circuit for the $[[4, 1, 2]]$ code correcting one data erasure (red cross). Colored boxes represent an ancilla-assisted measurement of a stabilizer associated with a plaquette of the same color. The ancilla is initialized in $| + ⟩$ , a sequence of $C X / C Z$ gates between the ancilla and the data qubits are applied (not shown), and the ancilla is measured in the Pauli $X$ basis. (c) The non-FT circuit for the $[[7, 1, 3]]$ code that is nonadaptive. An initial erasure error on a data qubit triggers the circuit, which measures all the six stabilizers in a fixed sequence (pink-green-blue) and applies the correction at the end. We explicitly show the $C X$ gates in the first box ( $X_{3} X_{4} X_{6} X_{7}$ stabilizer measurement) to illustrate an erasure error that propagates to multiple data errors and causes a logical failure. The top shows the evolution of the errors for the example trajectory. The red circles indicate qubits with potential Pauli errors (converted from the erasure errors). (d). The FT circuit for the $[[7, 1, 3]]$ corrects the errors adaptively. Suppose another erasure happens during the $C Z$ gate (shown in red) between the ancilla and the third qubit while measuring $Z_{1} Z_{2} Z_{3} Z_{4}$ . Upon detection of this error we stop the stabilizer measurement, discard and replace the ancilla and the third qubits and update the erasure-flag error set $E$ to $E = {I, X_{1}} \times {I, P_{3}} \times {I, Z_{1} Z_{2}}$ , where $P_{3}$ indicates an arbitrary Pauli error on the third qubit. The correlated $Z_{1} Z_{2}$ error results from discarding the ancilla that is entangled with the first and the second qubits. We then measure the stabilizers $X_{1} X_{2} X_{3} X_{4}$ , $X_{2} X_{3} X_{5} X_{6}$ , $Z_{2} Z_{3} Z_{5} Z_{6}$ , and $Z_{1} Z_{2} Z_{3} Z_{4}$ to correct possible errors within $E$ .
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Figure 3
The solid (dashed) lines show the lower (upper) bound of the lifetime with (without) the fault-tolerant implementation. The dotted line shows the expected lifetime $λ^{- 1}$ without error correction. The circle ( $[[4, 1, 2]]$ ) and square ( $[[7, 1, 3]]$ ) markers show estimates of the improved lifetime with error correction for maximal recovery time using experimentally feasible parameters.
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Figure 4
Detail of the coupling of the ancilla chip in Fig. 1 to a data chip. We show three surface patches $S$ (syndrome), $A$ (ancilla), and $D$ (data). Each patch is encoded in a rotated surface code, with data qubits on the vertices and $X$ -type ( $Z$ -type) syndrome qubits on the black (white) plaquettes. To extract error syndromes, a $C X$ gate between $S$ and $D$ patches is implemented by introducing the $A$ patch and applying the measurement-based circuit shown in the inset.
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