Logical Qubit in a Linear Array of Semiconductor Quantum Dots

We design a logical qubit consisting of a linear array of quantum dots, we analyze error correction for this linear architecture, and we propose a sequence of experiments to demonstrate components of the logical qubit on near-term devices. To avoid the difficulty of fully controlling a two-dimensional array of dots, we adapt spin control and error correction to a one-dimensional line of silicon quantum dots. Control speed and efficiency are maintained via a scheme in which electron spin states are controlled globally using broadband microwave pulses for magnetic resonance, while two-qubit gates are provided by local electrical control of the exchange interaction between neighboring dots. Error correction with two-, three-, and four-qubit codes is adapted to a linear chain of qubits with nearest-neighbor gates. We estimate an error correction threshold of ${10}^{-4}$. Furthermore, we describe a sequence of experiments to validate the methods on near-term devices starting from four coupled dots.

Popular Summary

The fragile nature of quantum computation makes it necessary to have mechanisms that recover from faults, and quantum experiments are close to reaching the complexity required to demonstrate fault-recovery techniques. To that end, researchers in universities, government labs, and private companies are racing to develop a logical qubit, a prototype of the first quantum processor to use active error correction. We show how to construct a logical qubit using small semiconductor devices known as quantum dots—a leading qubit technology that inherits many fabrication techniques developed for conventional integrated circuits and microprocessors.

Our analysis provides a practical approach to developing a logical qubit in the near future, including a focus on simple device designs built out of proven components, such as electrically tunable coupling of dots and electron spin resonance. We take the uncommon approach of designing a functioning logical qubit in a linear array of dots, which has the advantage of reducing device complexity compared to other proposals that require a two-dimensional array. We also lay out a path of experiments that demonstrate building blocks of error correction, providing a guiding strategy towards developing a logical qubit in quantum dots.

While we focus on the near-term fabrication of just a single logical qubit, our proposed quantum dot architecture has the potential to be extended to multiple logical qubits, paving the way for a practical, robust quantum computer.

Figure 1

Device schematic for a linear array of quantum dots. (a) Cross-section view of the device stack, with dots forming under metal gates. (b) Top view of the device where dispersive readout is implemented through the gate electrodes [89, 90, 91]. (c) Alternative top view where readout is implemented using single-electron transistors (SETs) located near the dots [27, 40]. This example has 14 dots, which corresponds to a logical-qubit demonstration described in Sec. 4.

Figure 2

Randomly generated sample of spread in $g$ factors for a linear chain of 20 quantum dots. The underlying distribution of $g$ factors is based on the measured variance in $g$ factors observed in devices like the one in Ref. [27]. Each data point shows the range of $g$-factor tuning possible with Stark shifting [27, 40, 101], corresponding to 10 MHz at $B=1.5\mathrm{T}$. Dots 5 and 6 are colored red to indicate that they have small $\mathrm{\Delta }g$ splitting and require the $g$ factors for those dots to be tuned apart for the cz gate, as described in the text.

Figure 3

Quantum circuit illustration of the dynamical decoupling scheme for the adiabatic controlled-phase gate; the controlled-$\sqrt{Z}$ pulses on two qubits in two dots are implemented via adiabatic pulsing of exchange. The resulting operation includes single-qubit $Z$ rotations; these are decoupled by the intervening single-qubit $\pi$ pulses about $X$, which may be implemented via a global ESR pulse.

Figure 4

Implementing a controlled-phase gate using exchange and $g$-factor differences. (a) The modeled functions of $g$-factor difference $\mathrm{\Delta }g(V)$ exchange rate $J(V)$ versus detuning voltage, employing typical parameters, similar to those demonstrated in Ref. [27]. (b) Pulse shapes for $\mathrm{\Delta }g[V(t)]$ and $J[V(t)]$, plotted on the same scale as panel (a), for a Gaussian detuning voltage pulse $V(t)\propto \exp (-t^2/2{\sigma }_t^2)$ for two different values of ${\sigma }_t$, including added voltage noise $\delta V(t)$ with spectral noise density $S_V(t)=A^2/f$. These sample traces use a rather high value of $A\sim 30\mu \mathrm{V}$ to allow the noise to be visible on this scale. (c) Simulated infidelity of the adiabatic cz gate. The red line results from simulating with no charge noise but examining infidelity due to nonadiabatic behavior. The cyan line considers strictly adiabatic evolution but adds charge noise by Monte Carlo integration using sampled voltage noise as in (a), in this example, with $A=5\mu \mathrm{V}$. The charge-noise-induced infidelity (cyan line) decreases due to exchange noise, for which the primary trend indicated by the blue line follows $10(A/I_{\mathrm{peak}}{)}^2$, where $I_{\mathrm{peak}}=J/|dJ/dV|$ is the insensitivity [50] at peak $J$. For longer pulses the charge-noise-induced infidelity increases due to noise on the $g$ factor; the green trend plot is $\int |\mathrm{\Delta }g[V(t)]{|}^{2}dt/(500\mathrm{Grad}/\sec )$. The thick gray line is the total infidelity, estimated as the sum of the diabaticity (red) and charge-noise (cyan) contributions.

Figure 5

Example of using tick-tock control to apply cnots to four spins, labeled Q1–Q4. (a) Original control sequence consisting of global Hadamard gates that demarcate transitions between tick and tock intervals, as well as selectively addressed cz gates within a tick or tock interval. (b) Equivalent circuit diagram where two Hadamard gates and a cz are merged to form a cnot, with grouping shown by dashed boxes. The convention is that cnot will have its control on an odd qubit in tick intervals (Op1, Op2, and Op5) and on an even qubit in tock intervals (Op3). When there is no intervening cz gate, Hadamards pair to identity (Op4 and Op6). As explained in the text, the unmatched Hadamard gates at the beginning and end of computation are not a concern.

Figure 6

Measurement gadgets using singlet preparation and measurement in the singlet-triplet basis, as follows: (a) $X$-basis measurement, (b) $Z$-basis measurement, (c) parity measurement of $X\otimes X$ on two data spins, and (d) parity measurement of $Z\otimes Z$ on two data spins. The gadget extends to measuring a $X$ or $Z$ operator of any size by adding cnot gates.

Figure 7

Device schematic and control sequence for the parity-measurement experiment. These diagrams show how an error-correction control sequence is mapped from circuits to operations on quantum dots. (a) Four exchange-coupled silicon dots with reservoir. (b) Parity measurement circuit using a singlet ancilla and measurement. The two-qubit gates are standard-LNN instructions, described in Sec. 3. This representation is convenient because it is compact, but an experiment must unpack each instruction into a sequence of ESR and exchange operations. (c) Tick-tock control sequence showing how the two-qubit gates in panel (b) are decomposed into cz entangling gates between the global Hadamards implemented by ESR. swap is decomposed into three cnots, and the cnot-followed-by-swap gate is two cnots, using a circuit identity [62]. (d) Sequence of electrostatic voltage biasing to implement the exchange-based cz gates, with step numbers corresponding to panel (c) and dots labeled Q1–Q4 as in the other panels. Composite gates such as those shown in steps 3–5 of panel (c) may require multiple exchange pulses, so what is depicted in panel (d) shows which spins are undergoing exchange.

Figure 8

Standard-LNN instructions and their circuit-diagram symbols. All of the instructions are available at the hardware level using tick-tock control, and they are native encoded operations for all CSS codes, including the codes in this proposal (note that magic-state preparation is not fault tolerant and is a subroutine for distillation using other standard-LNN instructions [126]). The five two-qubit gates are all combinations of cnot gates [62]. The instruction “free” differs from “idle” in that a free qubit (temporarily) has an undefined state and carries no information, whereas an idle qubit carries information. At the hardware level, the distinction may only be a labeling, but the instructions will have different encoded representations after code concatenation.

Figure 9

Tile for encoded cnot in the two-qubit bit-flip code. The cnot symbol in the upper left is a visual guide, and we use bit-flip or phase-flip to clarify when necessary. Input and output lines are labeled for convenience. Two code blocks $A$ and $B$ have their data qubits labeled with numeric subscripts. A core “swap diamond” of interleave, transversal cnot, and separate operations are shown with distinct colored backgrounds. Error detection using ancillas follows in a diagonal pass through the blocks. These ancillas begin and end on “free” lines that are not encoded at the lower layer, which are at different positions before and after the tile.

Figure 10

Half tiles for encoded measurement and preparation in the bit-flip code. (a) Half tile for measurement and preparation in the $Z$ basis. (b) Half tile for measurement and preparation in the $X$ basis, which requires the cnot for encoding a $|+⟩$ state. In both cases, dashed lines denote a qubit that is free, meaning its state is unimportant (and unencoded at lower layers). Equivalent operations in the phase-flip code are complementary, with encoded $|\overline{+}⟩$ preparation being separable into two $|+⟩$ preparations and $|\overline{0}⟩$ requiring the same quarter tile as the right-hand side of panel (b). Measurement operations are the same in the phase-flip code (i.e., implemented transversally).

Figure 11

Half tiles for state injection in the two-qubit codes, (a) bit-flip and (b) phase-flip. The preceding measurement is shown to complete the half tile, and the basis could be changed following Fig. 10. Importantly, this tile alone is not fault tolerant because the cnot can emit an undetected weight-two error. This is acceptable because the injection tile is used for magic states that must be distilled.

Figure 12

Half tile for idle in the phase-flip code. This shows the error-detection subcircuit for the phase-flip code.

Figure 13

Concatenation of distance-two repetition codes with tiles. A phase-flip idle tile (upper left) is encoded using the logical qubits of bit-flip codes. The operations in the half tile in the upper left are divided into tile instructions with dashed lines and numbered to correspond to the bit-flip tiles on the right.

Figure 14

Idle half tile for the three-qubit repetition code with phase-flip error detection. The figure is compressed laterally to save space, as denoted by the curved white slash. The left side of the tile has either idle or free segments that pad the width to match the cnot tile.

Figure 15

Encoded cnot for the three-qubit bit-flip code. The transversal cnot gates (yellow background) and swap gates to separate the blocks (green background) are broken up by an additional error-detection circuit that is inserted after the first round of swap gates to catch an otherwise uncorrectable error.

Figure 16

Half tiles for the three-qubit code, showing measurement and preparation in (a) the $Z$ basis and (b) the $X$ basis, as well as state injection for (c) the bit-flip code and (d) the phase-flip code. In the phase-flip code, preparing $|\overline{+}⟩$ is transversal, while $|\overline{0}⟩$ uses the state injection in panel (d) with $|\psi ⟩=|0⟩$.

Figure 17

Idle tile for four-qubit code. A Bell state $|{\mathrm{\Phi }}^{+}⟩=(|00⟩+|11⟩)/\sqrt{2}$ is used to measure the syndrome because it can also detect weight-two errors introduced by the error-detection circuit. The two-qubit ancilla is measured in the Bell basis (lower right, denoted “B”) to detect $X$ and $Z$ errors simultaneously.

Figure 18

Tile for measurement and preparation in Bell basis. The two operations can be implemented individually by replacing one with “free” instructions. The construction produces a pair of entangled logical qubits $|\overline{{\mathrm{\Phi }}^{+}}⟩=(|\overline{0}\overline{0}⟩+|\overline{1}\overline{1}⟩)/\sqrt{2}$ and requires modified syndrome processing, described in the Appendix.

Figure 19

cnot tile for the four-qubit subsystem code. As with the other codes, any combination of encoded cnots between the two blocks can also be implemented by modifying the gate in the center of the swap diamond.

Figure 20

Half tiles for measurement and preparation in the four-qubit code, in (a) the $X$ basis and (b) the $Z$ basis, as well as (c) state injection. As before, the measurement and preparation bases can be different by combining the appropriate subcircuits.

Figure 21

Simulated logical error rates for the two-qubit repetition code using concatenation. For all traces, the sequence of concatenation alternates bit-flip, phase-flip, etc. starting from lowest level. Two methods of simulation are employed: Monte Carlo error generation and malignant-set counting. The dots are Monte Carlo generation of errors at the specified physical error rate, using the error model described in the text. Error bars are 90% confidence intervals estimated from the data. The solid curves are produced by malignant-set counting or sampling, as described in the text; the logical error rate is given by Eq. (8), after the coefficients are estimated. The correspondence between the two methods is a consistency check. We explicitly verify that the level-four encoding corrects any single fault.

Figure 22

Simulated logical error rates for the four-qubit code using concatenation. As in Fig. 21, both Monte Carlo error generation and malignant-set counting are employed; the dots are Monte Carlo with error bars showing 90% confidence intervals, and the solid curves are malignant-set sampling. We explicitly verify that the level-two encoding corrects any single fault.

Figure 23

Summary of the experiments in this proposal. The names of the experiments on the left are grouped according to the subsections below. The middle columns show which of the criteria for an extensible logical qubit (see Introduction) are demonstrated by the experiment, denoted with green squares. In this context, the “error threshold” criterion means that one can demonstrate that error correction is functioning by purposefully inserting errors, as described in the text; the “fault tolerance” criterion means that any single bit-flip and/or phase-flip error is detectable. The diagrams on the right are simplified device layouts showing how many coupled dots are needed for the experiment, where data spins are shown in blue and ancilla spin pairs are shown in red and grouped.

Figure 24

Device schematic and control sequence to detect one type of error, such as a bit flip. (a) The five-dot device has one spin-pair ancilla (Q1 and Q2) and three data spins (Q3–Q5). (b) Control sequence to measure the bit parity of Q4 and Q5 ($ZZ$ parity). A complete implementation of the three-qubit code, as in Fig. 14, would require repeating this parity-detection circuit for this pair (Q4 and Q5) and the other pair of data spins (Q3 and Q4). Each of the swap and cnot operations are decomposed by tick-tock control, as shown in Fig. 7 and described in Sec. 2c. This experiment is similar to recent demonstrations in Refs. [24, 26, 28, 30].

Figure 25

Experimental setup to demonstrate concatenation of bit-flip and phase-flip error-detecting codes. (a) Linear array of 12 quantum dots. (b) Diagram for code concatenation with tiles, with spins from panel (a) labeled on the left side. For generality, the tiles in Sec. 3 represent measurable qubits with just one line, but in tick-tock control, the ancillas for measurement require spin pairs. These spin pairs begin as (Q3,Q4), (Q7,Q8), and (Q11,Q12), and they move during the experiment following this diagram. The spins could be initialized using techniques in Sec. 2c to test error detection, and the experiment can be extended to more rounds by adding more tiles.

Figure 26

Message passing between layers of encoding [6, 140], where layer $L$ is phase-flip encoded and layer $L+1$ is bit-flip encoded. After each tile in layer $L$ processes its syndrome, it passes a message containing information on logical errors to layer $L+1$. In this example, the first five tiles in layer $L$ have completed execution and syndrome processing; the extracted logical error channels are passed to layer $L+1$, denoted as ${ϵ}_1$ to ${ϵ}_5$. The remaining instructions from layer $L+1$ have not been executed, so the corresponding error channels are shown in grey with dashed borders. When all 12 error channels are available, the tile at layer $L+1$ will process its syndrome and pass an error message to the next layer above.

Figure 27

Error information used for syndrome processing in a tile. (a) Substitution to convert a two-qubit error channel to single-qubit channels, separating errors that are detected by the syndrome from undetected errors. (b) Location of error channels after substitution in a tile that is ready for syndrome processing. At the end (i.e., right side) of the tile, a few errors occur after syndrome processing, and they are not detected. These are passed as “residual” errors to the next tile, just as residual errors are passed into this tile from the left.