High current, 0.5-MA, fast, 100-ns, linear transformer driver experiments

The linear transformer driver (LTD) is a new method for constructing high current, high-voltage pulsed accelerators. The salient feature of the approach is switching and inductively adding the pulses at low voltage straight out of the capacitors through low inductance transfer and soft iron core isolation. Sandia National Laboratories are actively pursuing the development of a new class of accelerator based on the LTD technology. Presently, the high current LTD experimental research is concentrated on two aspects: first, to study the repetition rate capabilities, reliability, reproducibility of the output pulses, switch prefires, jitter, electrical power and energy efficiency, and lifetime measurements of the cavity active components; second, to study how a multicavity linear array performs in a voltage adder configuration relative to current transmission, energy and power addition, and wall plug to output pulse electrical efficiency. Here we report the repetition rate and lifetime studies performed in the Sandia High Current LTD Laboratory. We first utilized the prototype $\sim 0.4\mathrm{\text{−}}\mathrm{MA}$, LTD I cavity which could be reliably operated up to $\pm 90\mathrm{\text{−}}\mathrm{kV}$ capacitor charging. Later we obtained an improved 0.5-MA, LTD II version that can be operated at $\pm 100\mathrm{kV}$ maximum charging voltage. The experimental results presented here were obtained with both cavities and pertain to evaluating the maximum achievable repetition rate and LTD cavity performance. The voltage adder experiments with a series of double sized cavities (1 MA, $\pm 100\mathrm{kV}$) will be reported in future publications.

Figure 1

Top view of the prototype LTD I cavity. The top metal cover and plastic insulator which insulates the charged parts from the cavity walls are removed.

Figure 2

(a) Side section of a brick with a liquid resistor as a load. This is an actual reduction of the cavity assembly blueprint. (b) Schematic electrical diagram of the brick. The cavity components are: 1—switch; 2—capacitors; 3—plastic insulator plates; 4—ferromagnetic cores; 5—annular KBr liquid resistor load; 6—supporting nylon rod.

Figure 3

Pictorial representation of a side section of the LTD cavity where the load now is the coaxial line formed by the inner cylindrical surface of the cavity and the central (cathode) cylindrical electrode (at this representation double-ended capacitors are assumed). The red arrows show the current direction in each conductor.

Figure 4

Double-ended (left) and single-ended capacitors. The arrow indicates the high-voltage terminal. The other is the ground terminal. The single-ended capacitors are 7.5 cm longer in order to insulate the two electrodes that are side by side. In the figure above only the high-voltage terminal of the single-ended capacitor is shown; the other one is hidden by the plastic insulator plate.

Figure 5

Schematic diagram of the LTD cavity switch. The operating maximum voltage is $\pm 100\mathrm{kV}$ and the maximum current 25 kA. The switch components are: 1—cover flange; 2—cylindrical nylon housing; 3—spark gap electrodes; 4—tube for inlet and outlet; 5—rod holder of corona voltage grading needles. The dimensions are in mm. The cross section of the switch is taken through the middle electrode [11].

Figure 6

Photograph of the LTD cavity switch. The voltage grating electrodes of the switch can be seen as well as one of the gas switch input connected to the center electrode.

Figure 7

LTD cavity simplified equivalent circuit. The resistance $R$ is the sum of the load and internal circuit impedance. This circuit neglects the core losses.

Figure 8

LTD cavity equivalent circuit including core losses represented with the resistance $R_c$. Here $R_1$ and $L_1$ are the cavity total resistance and inductance and $L_2$ is the inductance of the load.

Figure 9

The High Current LTD Laboratory.

Figure 10

200 shots output pulse current overlay of the prototype LTD I cavity.

Figure 11

Comparison of three output current traces obtained of the prototype LTD I cavity with the SCREAMER circuit code calculations.

Figure 12

Typical load voltage trace compared with a Pspice [23] circuit code calculated voltage trace.

Figure 13

Self-break curve of the LTD switches.

Figure 14

Pictorial representation of the switch closure time (the time interval between the arrival of the trigger pulse on the switches and the start of the output pulse) as a function of the switch pressure.

Figure 15

Switch closure variation (jitter) for the switch pressure range studied.

Figure 16

Average pulse rise time as a function of switch pressure. The error bars represent the shot to shot statistical variation ($1\sigma$).

Figure 17

Average pulse fall time as a function of switch pressure. The error bars represent the shot to shot statistical variation ($1\sigma$).

Figure 18

Average output pulse full width at half maximum (FWHM) for a number of switch pressures. The charge voltage was always $\pm 100\mathrm{kV}$.

Figure 19

Average output pulse amplitude as a function of switch pressure. The error bars are the standard deviation of 100 shots for each pressure and are smaller than the size of the dots.