Voltage-controlled Hubbard spin transistor

Transistors are key elements for enabling computational hardware in both classical and quantum domains. Here we propose a voltage-gated spin transistor using itinerant electrons in the Hubbard model which acts at the level of single electron spins. Going beyond classical spintronics, it enables the controlling of the flow of quantum information between distant spin qubits. The transistor has two modes of operation, open and closed, which are realized by two different charge configurations in the gate of the transistor. In the closed mode, the spin information between source and drain is blocked while in the open mode we have free spin information exchange. The switching between the modes takes place within a fraction of the operation time which allows for several subsequent operations within the coherence time of the transistor. The system shows good resilience against several imperfections and opens up a practical application for quantum dot arrays.

Figure 1

(a) Schematic of the QST. In a 1D lattice, two electrons are extremely localized at source and drain sites and $n$ electrons hopping among $L$ sites of a central gate as a quantum channel. (b) and (c) Diagrams show how setting voltages can control the configurations of electrons for opening and closing the gate in the shortest possible transistor with size $L=3$ filled by $n=1$ electron.

Figure 2

(a) Dynamics of the average fidelity and logarithmic negativity $\chi$ in the shortest ($L=3$ and $n=1$) transistor with an open gate. The inset shows the performance of the transistor with a closed gate. The charge occupancy diagrams in the shortest transistor with an open (b) and closed (c) gate. In all plots, the potential landscape are tuned in optimal values ${\varepsilon }_{\text{open}}^{\text{opt}}=10t$, ${\varepsilon }_{\text{closed}}^{\text{opt}}=20t$, and ${\varepsilon }_{s,d}^{\text{opt}}=39t$ for both modes.

Figure 3

(a) Fidelity of transition ${\rho }_{\text{open}}$ into ${\rho }_{\text{closed}}$ at the end of the bias sweeping as a function of ${\tau }_{\text{sw}}$ which is a percentage of ${\tau }_L^{\text{opt}}$ for different gate length $L=3,5,8$ and $n=1$. Inset shows the transmission of the electron from the barriers to the middle of the gate by bias sweeping from ${\varepsilon }_k=|\lceil L/2\rceil -k|{\varepsilon }_{\text{open}}$ into the opposite bias ${\varepsilon }_k=(k-1){\varepsilon }_{\text{closed}}$ as a function of time in the shortest transistor with $n=1$. (b) Functionality of the shortest transistor with $L=3$ and $n=1$ for $M$ subsequent opening and closing the gate without resetting.

Figure 4

Charge occupancies of a gate of length $L=6$ filled by $n=3$ (a) and $n=4$ (b) electrons versus time. In all plots the chemical potential are tuned into their optimal values presented in Table 1.

Figure 5

Functionality of the shortest transistor filled by $n=1$ electron with open and closed gates as a function of the temperature $T{K}_B$ (a), disorder strength $\lambda$ (b), decoherence rate $\gamma$ (c), and SOC strength $\alpha$ (d). In these plots the parameters are tuned as ${\tau }^{\text{opt}}=64t$, ${\varepsilon }_{s,d}^{\text{opt}}=39t$, ${\varepsilon }_{\text{open}}^{\text{opt}}=10t$, and ${\varepsilon }_{\text{closed}}^{\text{opt}}=20t$.