Smallest Stable $\mathrm{Si}/{\mathrm{SiO}}_2$ Interface that Suppresses Quantum Tunneling from Machine-Learning-Based Global Search

While the downscaling of size for field effect transistors is highly desirable for computation efficiency, quantum tunneling at the $\mathrm{Si}/{\mathrm{SiO}}_2$ interface becomes the leading concern when approaching the nanometer scale. By developing a machine-learning-based global search method, we now reveal all the likely $\mathrm{Si}/{\mathrm{SiO}}_2$ interface structures from thousands of candidates. Two high Miller index Si(210) and (211) interfaces, being only $\sim 1\mathrm{nm}$ in periodicity, are found to possess good carrier mobility, low carrier trapping, and low interfacial energy. The results provide the basis for fabricating stepped Si surfaces for next-generation transistors.

Figure 1

Structures of FETs. (a) Classic planar FET; (b) modern FinFET. $L$ represents the channel length.

Figure 2

(a) The flowchart of the ML-interface method. (b) Atomic structures of ten $\mathrm{Si}/{\mathrm{SiO}}_2$ interfaces with an interfacial area less than $1{\mathrm{nm}}^2$ in periodicity. The dashed cycles in (b) highlight the unsatisfied Si atoms with dangling bonds. Yellow balls, Si; red balls, O.

Figure 3

(a),(b) Transmission coefficient vs incident energy for carrier tunneling through a 0.5-eV height potential barrier; (c) partial charge densities at CBM or VBM of ${(100)}_{\mathrm{Si}}\Vert {(111)}_{\alpha \text{−}\text{crist}}$, ${(111)}_{\mathrm{Si}}\Vert {(110)}_{\alpha \text{−}\text{crist}}$, and ${(331)}_{\mathrm{Si}}\Vert {(010)}_{\alpha \text{−}\text{crist}}$ interfaces.