Long-Time Memory and Ternary Logic Gate Using a Multistable Cavity Magnonic System

Multistability is an extraordinary nonlinear property of dynamical systems and can be explored to implement memory and switches. Here we experimentally realize the tristability in a three-mode cavity magnonic system with Kerr nonlinearity. The three stable states in the tristable region correspond to the stable solutions of the frequency shift of the cavity magnon polariton under specific driving conditions. We find that the system staying in which stable state depends on the history experienced by the system, and this state can be harnessed to store the history information. In our experiment, the memory time can reach as long as 5.11 s. Moreover, we demonstrate the ternary logic gate with good on-off characteristics using this multistable hybrid system. Our new findings pave a way towards cavity magnonics-based information storage and processing.

Figure 1

(a) Schematic of the three-mode cavity magnonic system, where two YIG spheres are glued on the walls of a microwave cavity. The transmission of the system is measured by the VNA via ports 1 and 2. The drive field is loaded to port 3. The bias magnetic field ${\mathbf{B}}_0$ is applied along the $z$ direction, and two local magnetic fields ${\mathbf{B}}_1$ and ${\mathbf{B}}_2$ are applied to separately tune the frequencies of the magnon modes 1 and 2. The inset panel in the cavity shows the magnetic-field distribution of the cavity ${\mathrm{TE}}_{102}$ mode. The microwave sources A and B serve as the two inputs of the logic gate. (b) Schematic of the multistability of CMP frequency shift. The gray area is the tristable region. The yellow star marks the state where we measure the memory effect of the multistable system. The blue, green, and red dots correspond to the logic output states 0, 1, and 2 of the ternary OR gate. The corresponding input drive powers are power off (0), 24 dBm (1), 30 dBm (2), respectively. (c) Symbol and truth table of the ternary OR gate.

Figure 2

Frequency shift ${\chi }_{\mathrm{UP}}$ of the upper-branch CMP versus the drive power $P_d$. The blue (green) triangles are the forward (backward) sweeping results. (a) ${\delta }_{\mathrm{UP}}/2\pi \equiv ({\omega }_{\mathrm{UP}}-{\omega }_d)/2\pi =-2$, (b) $-6$, (c) $-10$, and (d) $-18\mathrm{MHz}$. The red triangles are obtained by sweeping the drive power backward from 26 dBm, when the upper-branch CMP is in the middle stable state (MSS). The black curves are numerical results calculated using Eq. (2). The gray area depicts the tristable region. The yellow star indicates the state in which we measure the memory effect.

Figure 3

(a) The memory time measurement. The system is first prepared in the MSS located in the tristable region. The drive field is turned off and on to find out the maximum memory time (5.11 s). The inset is the schematic of the drive-power sweeping procedure. (b) The observed frequency-shift relaxation and fitting. The fitting equation is ${\chi }_{\mathrm{UP}}/2\pi =19.84e^{-{\mathrm{\Gamma }}_{\mathrm{UP}}t}\mathrm{MHz}$, which gives the relaxation rate ${\mathrm{\Gamma }}_{\mathrm{UP}}/2\pi =0.049\mathrm{Hz}$. (c) A sequence of switches with different power-off times. From left to right, they are 3.60, 4.20, 4.80, and 5.20 s, respectively. For the power-off time of 5.20 s, we find that the system can no longer recover to the MSS.

Figure 4

(a) Left panel: Schematic of the input levels. A strong (moderate) drive power represents the 2 (1) input, and the drive power off represents the 0 input. Right panel: The two inputs A and B are combined to drive the upper-branch CMP. To ensure the joint power equal to the larger input of the two inputs, we add a phase shifter in one of the channels and finely adjust the relative phase. (b) Top panel: The sequences of the ternary logic OR gate A-B inputs. Bottom panel: The corresponding outputs of the logic gate. The well-separated output levels 0, 1, and 2 correspond to the zero, small, and large frequency shifts of the upper-branch CMP.