Efficient Clocked Electron Transfer on Superfluid Helium

Unprecedented transport efficiency is demonstrated for electrons on the surface of micron-scale superfluid helium-filled channels by co-opting silicon processing technology to construct the equivalent of a charge-coupled device. Strong fringing fields lead to undetectably rare transfer failures after over a billion cycles in two dimensions. This extremely efficient transport is measured in 120 channels simultaneously with packets of up to 20 electrons, and down to singly occupied pixels. These results point the way towards the large scale transport of either computational qubits or electron spin qubits used for communications in a hybrid qubit system.

Figure 1

Micrograph showing a small central portion of the helium channel CCD where the electron clocking experiments are performed. Three of the 120 parallel horizontal channels are pictured, with a schematic cross section to the right of the image. The darker parts of the image are the channels with underlying gates, and the lighter parts are the topmost metal layer ridges between the channels. Electrons are confined above the helium-filled channels by a positive dc bias (3V) on the gates with respect to the top metal plane. Just visible on either side of the image are the left and right electron collection reservoirs, labeled “LR” and “RR”, with channel widths of $6$ and $3\mu \mathrm{m}$, respectively. The small gates in the horizontal channels between the right and left reservoirs have a $3\mu \mathrm{m}$ period including a $0.5\mu \mathrm{m}$ gap and are arranged as a 3-phase CCD, connected by on-chip vias to clock rails in a lower metal layer (drawn schematically below the micrographs). Each set of three CCD gates makes up one pixel for electron control. Exceptions to the 3-phase connections are the three gates closest to the right reservoir, which are labeled “twiddle”, “sense”, and “door” and serve as loading and detection gates. The cartoon image shows an electron on the helium surface in a cut-away view along the middle of a channel. The horizontal channels are interposed by two memory cells for electron storage and an interconnecting vertical CCD channel (clocked with voltages on $\varphi 2$, Vccd2, and Vccd3) for interchannel transport which are all $2.5\mu \mathrm{m}$ wide. All gates used in these experiments run under and control electrons in all 120 channels in parallel.

Figure 2

Measurement of the electron transfer efficiency along horizontal channels. The superimposed arrows in the inset image show the path electrons are clocked back and forth in the channels. The graph shows the electron signal measured at the correct pixel after a given number of CCD cycles, demonstrating an immeasurably low occurrence of transfer failure. The square data points were obtained in an experiment with about four electrons per packet (averaged over the 120 parallel channels), while the average packet size was less than one electron ($\sim 0.75$) for the experiment represented by the diamond data points.

Figure 3

Measurement of the electron transfer efficiency in 2D. The inset shows how electrons are cycled in a C pattern in the horizontal and vertical channels. The graph plots the measured signal from electrons which return to the correct pixels after a given number of cycles. The channel occupancy is calculated by dividing the calibrated signal by 60 (instead of 120 channels) because electrons in the upper 60 channels are ejected during the first instance of the C pattern. Two data sets are shown depicting experiments performed with different initial pixel populations.