Fault Tolerance with Noisy and Slow Measurements and Preparation

It is not so well known that measurement-free quantum error correction protocols can be designed to achieve fault-tolerant quantum computing. Despite their potential advantages in terms of the relaxation of accuracy, speed, and addressing requirements, they have usually been overlooked since they are expected to yield a very bad threshold. We show that this is not the case. We design fault-tolerant circuits for the 9-qubit Bacon-Shor code and find an error threshold for unitary gates and preparation of $p_{(p,g)\mathrm{thresh}}=3.76\times {10}^{-5}$ (30% of the best known result for the same code using measurement) while admitting up to $1/3$ error rates for measurements and allocating no constraints on measurement speed. We further show that demanding gate error rates sufficiently below the threshold pushes the preparation threshold up to $p_{(p)\mathrm{thresh}}=1/3$.

Figure 1

Measurement-free QEC routines for the QR and BS code. The inputs are $|{\overrightarrow{0}}^{(k)}⟩=|000{⟩}^{\otimes 3^{k-1}}$ and $|{\overrightarrow{+}}^{(k)}⟩=|+++{⟩}^{\otimes 3^{k-1}}$. (a) The $\mathcal{M}$ gate. An X-encoded majority voting gadget of level ($k+1$) of concatenation. Here all CNOTs are bitwise; i.e., each CNOT depicted corresponds to three $\mathrm{CNOT}(k)$, and subscript $R$ corresponds to a cyclic $k$-encoded rotation of the targets of the corresponding gate. In the QR code the TOFFOLI gate depicted is bitwise. The $\mathcal{M}$ gate can also be designed for a $Z$-encoded quantum majority voting, with $|{\overrightarrow{+}}^{(k)}⟩$ ancillas and the obvious Hadamard conjugation of gates. When the need to distinguish them arises, we shall denote $X$- and $Z$-encoded majority votings ${\mathcal{M}}^{(X)}$ and ${\mathcal{M}}^{(Z)}$, respectively. (b) A subroutine acting on ancilla for processing error syndrome information extracted from the data. The circuit shows one row, $(V\mathcal{N}{)}_i(k)$, of the fully contracted exRec $V\mathcal{N}(k)$ representing a collection of $k$-level protected gates acting on row $i$ of ancilla which take part in an $\mathrm{EC}(k+1)$ step. Note that in this circuit the output top lines are discarded so no EC gadget must protect them. With this, the exRec corresponding to $\mathcal{N}$ at degree of concatenation $k$ is $\mathcal{N}(k)=\mathrm{EC}(k)\times \prod _{i\in \mathrm{rows}}(V\mathcal{N}{)}_i(k-1)\times \mathrm{EC}(k)$. In our circuits $\lfloor G(k)\rfloor$ denotes the implementation of gate $G$, in terms of level-($k-1$) gates, without the prepended and appended $\mathrm{EC}(k)$ routines, and $W$ denotes a waiting gate. (c) Full EC gadget for the BS code. Here, a TOFFOLI with ◇ controls is a $Z\mathrm{\text{−}}\mathrm{TOFFOLI}$; $CX=\prod _{i,j=1}^3{\mathrm{CNOT}}_{(c,i,j),(t,i,j)}^{(k)}$ is a set of transversal CNOTs, $C{X}_{P_R}^{(\pm )}=\prod _{i,j=1}^3{\mathrm{CNOT}}_{(c,i,j),(t,i\pm 1j)}^{(k)}$, and $C{X}_{(\pm )}^{P_C}=\prod _{i,j=1}^3{\mathrm{CNOT}}_{(c,ij\mp 1),(i,j)}^{(k)}$. The control of the gates in boxes is always the top input of the gate. The last gate is a $b\mathrm{TOFFOLI}$.

Figure 2

These circuits need to be implemented only at the highest level of concatenation, and thus all operations depicted are encoded operations. (a) Circuit used to execute an encoded $Z^{1/2}$ Clifford gate on an arbitrary input $|{\varphi }_L⟩$ [17]. (b) Circuit implementing the non-Clifford operation $Z^{1/4}$ given the encoded resource magic state $|H_L⟩$.