Characterization of grain boundary impedances in fine- and coarse-grained $\mathrm{Ca}{\mathrm{Cu}}_3{\mathrm{Ti}}_4{\mathrm{O}}_{12}$ ceramics

The influence of electrode material, dc bias, and pellet thickness on the electrical properties of fine- and coarse-grained $\mathrm{Ca}{\mathrm{Cu}}_3{\mathrm{Ti}}_4{\mathrm{O}}_{12}$ (CCTO) ceramics has been investigated using impedance spectroscopy. The low frequency arc observed in ${\mathrm{Z}}^{*}$ plots near room temperature is independent of the electron work function of the metal electrode. It shows significant variation with dc bias and pellet thickness for coarse-grained ceramics, but no such variations for fine-grained ceramics. The results demonstrate the importance of ceramic microstructure in controlling the electrical properties of CCTO ceramics and support the internal barrier layer capacitor (IBLC) model of Schottky barriers at the grain boundaries between semiconducting grains. The IBLC model explains the high permittivity and nonlinear current-voltage characteristics commonly reported for CCTO ceramics.

Figure 1

Equivalent circuit (a) and schematic ${\mathrm{Z}}^{*}$ plot (b) for CCTO ceramics.

Figure 2

Illustration of a back-to-back double Schottky barrier at a single grain boundary when (a) $V=0$ and (b) $V>0$.

Figure 3

SEM micrographs of CCTO ceramics sintered at $1100°\mathrm{C}$ in air for $3\mathrm{h}$ (a) and $24\mathrm{h}$ (b).

Figure 4

${\mathrm{Z}}^{*}$ plot $(\sim 85°\mathrm{C})$ of a coarse-grained CCTO ceramic with InGa electrodes and Au electrodes (a) and corresponding $C^{\prime }$ spectroscopic plot (b).

Figure 5

Arrhenius plot of bulk and grain boundary conductivity data vs temperature for CCTO ceramics with InGa and Au electrodes.

Figure 6

$Z^{*}$ plot of data obtained for a coarse-grained CCTO ceramic with a dc bias of 0 and $15\mathrm{V}$ (a) and corresponding $M^{″}$ spectroscopic plots (b).

Figure 7

$R_{\mathrm{gb}}$ and $R_b$ vs dc bias (a) and $C_{\mathrm{gb}}$ vs dc bias (b) for a coarse-grained CCTO ceramic. Note: below a dc bias of $2\mathrm{V}$ it was not possible to observe the arc maximum in the ${\mathrm{Z}}^{*}$ plot (and therefore the corresponding Debye peak maximum in the $M^{″}$ spectroscopic plots) as it occurred below the lower frequency limit of the impedance analyzer, therefore data for $R_{\mathrm{gb}}$ and $C_{\mathrm{gb}}$ are restricted to dc bias $⩾2\mathrm{V}$.

Figure 8

${(1∕\mathrm{C}-1∕2{\mathrm{C}}_0)}^2$ vs $V$ for a coarse-grained CCTO ceramic. Note: The number of grain boundaries parallel to electrodes in this sample was estimated to be 20 (pellet $\sim 2\mathrm{mm}$ thick with an average grain size of $\sim 100\mu \mathrm{m}$). The dc bias has been divided by 20 to give an $x$ axis of applied voltage per grain boundary.

Figure 9

Arrhenius plots of grain boundary conductivity as a function of dc bias for coarse-grained CCTO ceramics.

Figure 10

Variation of $R_{\mathrm{gb}}$, $C_{\mathrm{gb}}$ and $R_b$ for a fine-grained CCTO ceramic as a function of dc bias.

Figure 11

$R_{\mathrm{gb}}$, $R_b$ and $C_{\mathrm{gb}}$ as a function of pellet thickness for coarse- and fine-grained CCTO ceramics (a) and (b), respectively.