Majorana-based quantum computing in nanowire devices

The boundary of one-dimensional topological superconductors might lead to the appearance of Majorana zero modes, whose nontrivial exchange statistics can be used for quantum computing. In branched nanowire networks, one can exchange Majorana modes by time dependently tuning topologically nontrivial parameter regions. In this paper, we simulate the exchange of four Majorana modes in T-shaped junctions made out of $p$-wave superconducting Rashba wires. We derive concrete experimental predictions for (quasi-)adiabatic braiding times and determine geometric conditions for successful Majorana exchange processes. Moreover, we prove that, in the adiabatic limit, the gating time needs to be smaller than the inverse of the squared superconducting order parameter and scales linearly with the gating potential. Furthermore, we show how to circumvent the formation of additional Majorana modes in branched nanowire systems, arising at wire intersection points of narrow junctions. Finally, we propose a multiqubit setup, allowing for universal quantum computing.

Figure 1

Setup. Structure of a tTt device, consisting of four nanowires. The chemical potential on each site can be controlled by a “keyboard” gate. Inner and outer T/t structures are characterized by the amount of lattice sites $N_{\mathrm{leg}}^{\mathrm{T}}$ and $N_{\mathrm{leg}}^{\mathrm{t}}$. Moreover, ${\mathrm{CP}}_{1–3}$ denote nanowire intersection points, and red (blue) regions encode topologically nontrivial (trivial) junction parts with associated MF modes ${\gamma }_{1–4}$. Steps 0–12 characterizes the exchange protocol ${\gamma }_1\leftrightarrow {\gamma }_2$. With $N_{\mathrm{leg}}^{\mathrm{t}}=2,N_{\mathrm{leg}}^{\mathrm{T}}=3$, and $N_{\mathrm{gate}}=1$, the exchange is realized in 12 steps, corresponding to the different keyboard gate configurations.

Figure 2

Exchange protocol ${\gamma }_2\leftrightarrow {\gamma }_3$. With $N_{\mathrm{leg}}^{\mathrm{t}}=2,N_{\mathrm{leg}}^{\mathrm{T}}=3$, and $N_{\mathrm{gate}}=1$, the braiding is realized in 22 exchange steps, corresponding to different keyboard gate configurations. The red (blue) regions encode topologically nontrivial (trivial) junction parts with associated Majorana modes ${\gamma }_{1–4}$.

Figure 3

The three lowest gaps of a thin t junction, formed by a nontrivial horizontal and a trivial vertical nanowire are shown as a function of the ${\mathrm{CP}}_1$ on-site potential $\delta \mu$. For $\delta \mu =0$, one observes the formation of additional subgap states, a property which can be corrected by applying $\delta {\mu }_{\mathrm{corr}}$.

Figure 4

Analytically and numerically determined values of $|\delta {\mu }_{\mathrm{corr}}|$ as a function of $\mathrm{\Delta }\mu$. For $\mathrm{\Delta }\mu =0$, one exactly has to correct the additional $t_{\mathrm{hop}}/a^2{\mathrm{CP}}_1$ hopping contribution.

Figure 5

Bound-state energy $\mathrm{\Delta }{E}_{\mathrm{BS}}(\mathrm{\Delta }\mu =\delta \mu =0)$ in a InSb-based t junction as a function of the wire width $W.|{\mathrm{\Delta }}_{\mathrm{sc}}|$ denotes the $s$-wave gap. For $W\approx 90\mathrm{nm},\mathrm{\Delta }{E}_{\mathrm{BS}}(\mathrm{\Delta }\mu =\delta \mu =0)$ starts to exceed $|{\mathrm{\Delta }}_{\mathrm{sc}}|$, coming along with ${\mathrm{CP}}_1$ bound states.

Figure 6

(a) Absolute value and argument of ${\left[{\kappa }_{12}\left(T\right)\right]}_{11}$ as a function of $L_{\mathrm{leg}}^{\mathrm{t}}$ for an (quasi-)adiabatic braiding ${\gamma }_1\leftrightarrow {\gamma }_2$ with $L_{\mathrm{Gate}}=L_{\mathrm{leg}}^{\mathrm{t}}$ and $L_{\mathrm{leg}}^{\mathrm{T}}=6\mu \mathrm{m}$. With increasing $L_{\mathrm{leg}}^{\mathrm{t}},\mathrm{Arg}\left\{{\left[{\kappa }_{12}\left(T\right)\right]}_{11}\right\}$ approximates the theoretical prediction of $\pi /2$. (b) $|{\left({\kappa }_{12}\left(T\right)\right)}_{11}|$ and (c) $\mathrm{Arg}\left\{{\left[{\kappa }_{12}\left(T\right)\right]}_{11}\right\}\left[\pi \right]$ as a function of $t_{\mathrm{step}}$ for several values $L_{\mathrm{leg}}^{\mathrm{T}}\ge L_{\mathrm{leg}}^{\mathrm{t}}=L_{\mathrm{Gate}}$. For all geometries and large $t_{\mathrm{step}}$, both quantities approximate their theoretical prediction. In the limit of small $t_{\mathrm{step}}$, non- (quasi-)adiabatic effects lead to deviations from this limit. (d) $\overline{\mathrm{abs}}\left(T\right)$ and $\mathrm{Arg}\left\{{\left[{\kappa }_{23}\left(T\right)\right]}_{\alpha ,\beta }\right\}\left[\pi \right]$ with $\{\alpha ,\beta \}\in \{1–4\}$ are shown as a function of $t_{\mathrm{step}}$ for $L_{\mathrm{leg}}^{\mathrm{T}}=2L_{\mathrm{leg}}^{\mathrm{t}}=2L_{\mathrm{gate}}=6\mu \mathrm{m}$. The curves $\mathrm{Arg}\left\{{\left[{\kappa }_{12}\left(t_{\mathrm{step}}\right)\right]}_{\alpha ,\beta }\right\}\left[\pi \right]$, denoted in the form ($\alpha ,\beta$, color), are given by (1,1, $\mathrm{orange},•$), (2,2, brown, $⧫$), (3,3, $\mathrm{lightblue},★$), (4,4, yellow, $▾$), (1,2, purple, $\blacksquare$), (1,3, black), (2,3, red), (1,4, pink), (2,4, blue) and (3,4, gray). The average value $\overline{\mathrm{abs}}\left(T\right)$ is shown in green. In the (quasi-)adiabatic regime, all quantities approximate their theoretical predictions.

Figure 7

Hardware setup of a cnot gate. We show the world lines of all MF modes during this operation [89]. Between the two outer tTt building blocks, defining the logical qubits by their MF modes ${\gamma }_{1–4}$ and ${\gamma }_{9–12}$, one has to implement another tTt building block, hosting the ancillary MF modes ${\gamma }_{5–8}$. Blue sites indicate topologically trivial, whereas red ones encode topologically nontrivial regions. The single tTt junctions are separated by $N_{\mathrm{spacer}}$ lattice sites, satisfying Eq. (5). ${\mathrm{\Pi }}_{1–3}$ represent nondestructive parity measurements with outcome $p_{1–3}$.

Figure 8

Preparation of a “noisy” copy of $|a_4\rangle$, based on the short-range interaction of two MF modes during the time $\tau$ [82].

Figure 9

$\pi /8$ phase gate with $|a_4\rangle \equiv \left(\right|\overline{0}\rangle +e^{i(\pi /4)}|\overline{1}\rangle )/\sqrt{2}$, $K\left(p_1\right)\equiv e^{-i(\pi /8){\sigma }_z(1-p_1)}$ and ${\sigma }_x\left(p_1\right)\equiv e^{i(\pi /4){\sigma }_x(1-p_1)}$. $p_1=\pm 1$ represent measurement results of $P_1={\sigma }_z\otimes {\sigma }_z$, which are transported via classical channels to the subsequent gates [83].

Figure 10

Hardware setup of a two-qubit system, allowing for universal QC algorithms. The two outer tTt building blocks define the logical qubits $|{\psi }_{1,2}\rangle$ via their MF modes ${\gamma }_{1–4}$ and ${\gamma }_{17–20}$. To enable a $\pi /8$ gate for each logical qubit, one has to generate $|a_4\rangle$ in the middle tTt structure. This state is distilled in the top 15 tTt building blocks via a [15,1,3] Reed-Muller code and finally transferred to the ancillary qubit structure, defined by ${\gamma }_{9–12}^{\prime }$. cnot operations between $|{\psi }_1\rangle$ and $|{\psi }_2\rangle$ or between $|{\psi }_{1,2}\rangle$ and $|a_4\rangle$ can be realized via the two ancillary tTt blocks, hosting the eight MF modes ${\gamma }_{5–8}$ and ${\gamma }_{13–16}$. They are initialized as stabilizer states $|\tilde{0}\rangle$. Blue sites indicate topologically trivial parameter regions, whereas red ones encode a topologically nontrivial ones. Green sites initially define topologically trivial junction parts as well. To enable nondestructive, projective-parity measurements, the device is connected to several top-transmon circuits.