Tunneling mechanism in a (Ga,Mn)As/GaAs-based spin Esaki diode investigated by bias-dependent shot noise measurements

Electron transport across a tunneling barrier is governed by intricate and diverse causes such as interface conditions, material properties, and device geometries. Here, by measuring the shot noise, we investigate electron transport in a (Ga,Mn)As/GaAs-based spin Esaki diode junction over a wide range of bias voltage. The asymmetric electronic band profile across the junction allows us to tune the types of tunneling process. By changing the bias voltage in a single device, we successively address the conventional direct tunneling, the excess current conduction through the mid-gap localized states, and the thermal excitation current conduction. These observations lead to a proper comparison of the bias dependent Fano factors. While the Fano factor is unity for the direct tunneling, it is pronouncedly reduced in the excess current region. Thus, we have succeeded in evaluating several types of conduction process with the Fano factor in a single junction.

Figure 1

(a) Schematic illustration of our lateral spin valve devices with two spin Esaki junctions (J1 and J2). Right panel shows the band diagram of the (Ga,Mn)As/GaAs epitaxial multilayer stacks and energy of electrons. In the electron band diagram, the vertical dashed green line represents the Fermi energy. (b) Current-voltage (I-V) characteristics of each spin Esaki diode junctions. (c)–(f) Energy diagrams for several bias voltage conditions; the red dashed arrows sketch typical transport mechanisms, where (c), (d), (e), and (f) correspond to the bias regimes (i), (ii), (iii), and (iv) in (b), respectively.

Figure 2

Schematics of the noise measurement setups including the equivalent circuit of the sample (see text for detail). By using a homemade sample holder, the low-temperature resistors and a capacitor are placed very close to the sample.

Figure 3

(a) $I$ and $R_{\mathrm{d}1}$ of junction J1 as a function of bias voltage. (b) Measured $S_I$ in Setup S and calculated full-shot noise ($2eI$). (c) Estimated $F$($\equiv S_I/2eI$) by using the data in (b).

Figure 4

(a) $I-V$ characteristics of the junctions in series as a function of a bias voltage for parallel (P) and antiparallel (AP) configurations. The right axis shows $R_{\mathrm{d}1}$ and $R_{\mathrm{d}2}$ of each junction for P configuration. (b) Measured $S_I$ in Setup D for P and AP. The solid and dashed lines show two shot noise limits. (c) Estimated $F$($\equiv S_I/2eI$) by using the data in (b).