Conditional Dispersive Readout of a CMOS Single-Electron Memory Cell

Quantum computers require interfaces with classical electronics for efficient qubit control, measurement, and fast data processing. Fabricating the qubit and the classical control layer using the same technology is appealing because it will facilitate the integration process, improving feedback speeds and offering potential solutions to wiring and layout challenges. Integrating classical and quantum devices monolithically, using complementary metal-oxide-semiconductor (CMOS) processes, enables the processor to profit from the most mature industrial technology for the fabrication of large-scale circuits. We demonstrate a CMOS single-electron memory cell composed of a single quantum dot and a transistor that locks charge on the quantum-dot gate. The single-electron memory cell is conditionally read out by gate-based dispersive sensing using a lumped-element $LC$ resonator. The control field-effect transistor (FET) and quantum dot are fabricated on the same chip using fully depleted silicon-on-insulator technology. We obtain a charge sensitivity of $\delta q=95\times {10}^{-6}e{\mathrm{\text{Hz}}}^{-1/2}$ when the quantum-dot readout is enabled by the control FET, comparable to results without the control FET. Additionally, we observe a single-electron retention time on the order of a second when storing a single-electron charge on the quantum dot at millikelvin temperatures. These results demonstrate first steps towards time-based multiplexing of gate-based dispersive readout in CMOS quantum devices opening the path for the development of an all-silicon quantum-classical processor.

Figure 1

Experimental setup and dc transport measurements: (a) Measurement circuit schematic, including SEM micrographs of the control FET and quantum device. Control and measurement signals are sent to the quantum device via the channel of a control FET. (b) Transport through the quantum device as a function of $V_{\mathrm{DL}}$ and $V_{\mathrm{WL}}$ yielding the threshold voltage of the control FET and quantum device at $V_{\mathrm{BG}}=0\mathrm{V}$. (c) Turn-on characteristic of the quantum device as a function of $V_{\mathrm{BG}}$ when the FET is biased well above threshold at $V_{\mathrm{WL}}=1.3\mathrm{V}$. (d) Cross-section illustration of the nanowire-based quantum device under high back-gate bias and near-threshold top-gate bias, such that a single quantum dot forms. (e) Coulomb diamonds indicating a single quantum dot in the quantum device at $V_{\mathrm{BG}}=10\mathrm{V}$.

Figure 2

rf characterization and charge sensitivity: (a) $S_{11}$ of the rf circuit as a function of $V_{\mathrm{WL}}$ (with $V_{\mathrm{DL}}=0.4\mathrm{V}$ and $V_{\mathrm{BG}}=10\mathrm{V}$). (b) Total resonator capacitance $C_T$ (with $L=390\mathrm{nH}$) and quality factor $Q$ as a function of $V_{\mathrm{WL}}$. (c) Change in phase response for different $V_{\mathrm{WL}}$ values showing three Coulomb oscillations only when the control FET is operated above threshold. Features originating from charge transitions within the control FET itself are indicated (as asterisk). (d) Coulomb diamonds measured in the phase response ($V_{\mathrm{BG}}=10\mathrm{V}$ and $V_{\mathrm{WL}}=1.3\mathrm{V}$), which is normalized with respect to the maximal change.

Figure 3

Charge sensitivity of the gated rf readout: (a) Sidebands in the spectrum when operating at the point of maximum slope of a Coulomb oscillation with an equivalent excitation of $0.00578e$ at 303 Hz superimposed on the data line. Signal-to-noise ratio (SNR) as a function of (b) data-line dc voltage $V_{\mathrm{DL}}$, (c) carrier frequency $f_{\mathrm{rf}}$, (d) carrier power $P_{\mathrm{rf}}$, and (e) FET gate voltage $V_{\mathrm{WL}}$. When not being swept, the following parameter values are used: $V_{\mathrm{WL}}=1.3\mathrm{V}$, $V_{\mathrm{DL}}=0.525\mathrm{V}$, $f_{\mathrm{rf}}=312\mathrm{MHz}$, $P_{\mathrm{rf}}=-85\mathrm{dBm}$.

Figure 4

Charge retention time and fast switching: (a) Equivalent circuit consisting of the variable control FET resistance $R_F$ and quantum device gate leakage $R_G$ and capacitance $C_G$. (b) Voltage divider characteristic of this circuit. (c) Demonstration of charge locking for different FET off states. Slow leakage of quantum-dot gate charge is observed. (d) Quantum device transfer characteristic. (e) Demonstration of rf sensing combined with fast switching of the control FET. Initially, the FET is biased above threshold and $V_{\mathrm{DL}}$ is ramped from 0.46 to 0.50 V. Tunneling of the first electron onto the quantum dot is observed (left axis). After 7.5 ms, the FET is biased below threshold, leading to a large jump in phase due to the change in resonance frequency (right axis), while $V_{\mathrm{DL}}$ is ramped back down. In the off state, no electron tunneling is observed.

Figure 5

Impact of FET resistance on the sensitivity to device capacitance changes: (a) Equivalent circuit with the FET resistance $R_{\mathrm{FET}}$, parasitic and FET capacitance $C_p$, and quantum device with losses $R_G^{\mathrm{rf}}$, capacitance $C_G$, and variable tunneling capacitance $C_t$. (b) Reflection coefficient sensitivity to capacitance changes as a function of $R_{\mathrm{FET}}$ for different values of $R_G^{\mathrm{rf}}$ (logarithmic scale). (Inset) Linear scale of region of low resistance.