Nonvolatile Multilevel Memory and Boolean Logic Gates Based on a Single $\mathrm{Ni}/[\mathrm{Pb}({\mathrm{Mg}}_{1/3}{\mathrm{Nb}}_{2/3}){\mathrm{O}}_3{]}_{0.7}[{\mathrm{PbTiO}}_3{]}_{0.3}/\mathrm{Ni}$ Heterostructure

Memtranstor that correlates charge and magnetic flux via nonlinear magnetoelectric effects has a great potential in developing next-generation nonvolatile devices. In addition to multilevel nonvolatile memory, we demonstrate here that nonvolatile logic gates such as nor and nand can be implemented in a single memtranstor made of the $\mathrm{Ni}/\mathrm{PMN}\text{−}\mathrm{PT}/\mathrm{Ni}$ heterostructure. After applying two sequent voltage pulses ($X_1$, $X_2$) as the logic inputs on the memtranstor, the output magnetoelectric voltage can be positive high (logic 1), positive low (logic 0), or negative (logic 0), depending on the levels of $X_1$ and $X_2$. The underlying physical mechanism is related to the complete or partial reversal of ferroelectric polarization controlled by inputting selective voltage pulses, which determines the magnitude and sign of the magnetoelectric voltage coefficient. The combined functions of both memory and logic could enable the memtranstor as a promising candidate for future computing systems beyond von Neumann architecture.

Figure 1

The Principle of the memtranstor. (a) The full diagram of fundamental circuit elements. The four linear elements (resistor, capacitor, inductor, and transtor) are defined by the linear relationships between two of four basic variables ($v$, $i$, $q$, $\phi$), respectively. The four memelements (memristor, memcapacitor, meminductor, and memtranstor) are defined by the nonlinear relationships between two variables, respectively. (b) The typical structure of a memtranstor. The $q\text{−}\phi$ relationship is realized via the ME coupling between magnetization ($M$) and polarization ($P$). (c),(d) The characteristics of memtranstors. Either butterfly-shaped or pinched hysteresis loops can be observed, depending on the magnitude of external stimulus. The different states of transtance, $T=dq/d\phi$, or equivalently, the ME voltage coefficient ${\alpha }_E=dE/dH$, ranging from positive to negative and high to low, are used to implement both nonvolatile memory and logic functions.

Figure 2

Multilevel nonvolatile memory based on the $\mathrm{Ni}/\mathrm{PMN}\text{−}\mathrm{PT}/\mathrm{Ni}$ memtranstor. (a) The structure of the device and the measurement configuration. Two layers of Ni are deposited on the surfaces of the PMN-PT(110) single crystal. The electric field is applied vertically to switch the ferroelectric domains and the magnetic field is applied in plane to control magnetic domains. (b) The ME voltage coefficient ${\alpha }_E$ as a function of dc magnetic field with the PMN-PT layer prepoled to $+P_s$ and $-P_s$, respectively. The states of ${\alpha }_E$ depend on the relative orientation between magnetic and ferroelectric domains. The large hysteresis with a high remnant ${\alpha }_E$ at zero dc bias is beneficial for practical applications. (c) Repeatable multilevel switch of ${\alpha }_E$ by applying selective voltage pulses ($-80$, 100, 58, and 52 V), in the zero-dc-bias magnetic field. After each voltage pulse (10 ms) ${\alpha }_E$ is measured for 100 s.

Figure 3

Nonvolatile nor logic based on a single memtranstor—the first mode. (a) The schematic of the device structure and operations. After initialization, two sequent voltage pulses $X_1$ and $X_2$ are inputted into the device to do the computation. The low input (10 V) is set as logic 0 and the high input (100 V) as logic 1. The result is read out by applying a small in-plane magnetic field ($\mathrm{\Delta }H$) to generate the output voltage via the ME effect. (b) The truth table of nor operation. (c) Experimental results obtained on the $\mathrm{Ni}/\mathrm{PMN}\text{−}\mathrm{PT}/\mathrm{Ni}$ memtranstor demonstrating the nor operation. The output positive ME voltage is set as logic 1 and negative as logic 0. Inputting logic 0 does not alter the ferroelectric domains so that the output ME voltage remains positive high. Inputting logic 1 fully reverses the ferroelectric domains so that the output ME voltage becomes negative.

Figure 4

Nonvolatile nor logic based on a single memtranstor—the second mode. (a) The schematic of the device structure and logic operations. After initialization, two sequent voltage pulses $X_1$ and $X_2$ are inputted into the device to do the computation. The low input (10 V) is set as logic 0 and the high input (60 V) as logic 1. The result is read out by applying a small in-plane magnetic field ($\mathrm{\Delta }H$) to generate the output voltage via the ME effect. (b) The truth table of nor operation. (c) Experimental results obtained on the $\mathrm{Ni}/\mathrm{PMN}\text{−}\mathrm{PT}/\mathrm{Ni}$ memtranstor demonstrating the nor operation. The output high ME voltage is set as logic 1 and low or negative as logic 0. Inputting logic 0 does not alter the ferroelectric domains so that the output ME voltage remains positive high. Inputting logic 1 partially reverses the ferroelectric domains so that the output ME voltage becomes low.

Figure 5

Nonvolatile nand logic based on a single memtranstor. (a) The schematic of the device structure and logic operations. After initialization, two sequent voltage pulses $X_1$ and $X_2$ are inputted into the device to do the computation. The low input (10 V) is set as logic 0 and the high input (58 V) as logic 1. (b) The truth table of nand operation. (c) Experimental results obtained on the $\mathrm{Ni}/\mathrm{PMN}\text{−}\mathrm{PT}/\mathrm{Ni}$ memtranstor demonstrating the nand operation. The output positive ME voltage is set as logic 1 and negative as logic 0. Inputting logic 0 does not alter the ferroelectric domains so that the output ME voltage remains positive high. Inputting a single logic 1 partially reverses the ferroelectric domains so that the output ME voltage reduces but still retains positive voltage. Only after inputting two logic 1s, the majority of ferroelectric domains are reversed so that the output ME voltage becomes negative.