Hybrid Spintronic-CMOS Spiking Neural Network with On-Chip Learning: Devices, Circuits, and Systems

Over the past decade, spiking neural networks (SNNs) have emerged as one of the popular architectures to emulate the brain. In SNNs, information is temporally encoded and communication between neurons is accomplished by means of spikes. In such networks, spike-timing-dependent plasticity mechanisms require the online programing of synapses based on the temporal information of spikes transmitted by spiking neurons. In this work, we propose a spintronic synapse with decoupled spike-transmission and programing-current paths. The spintronic synapse consists of a ferromagnet–heavy-metal heterostructure where the programing current through the heavy metal generates spin-orbit torque to modulate the device conductance. Low programing energy and fast programing times demonstrate the efficacy of the proposed device as a nanoelectronic synapse. We perform a simulation study based on an experimentally benchmarked device-simulation framework to demonstrate the interfacing of such spintronic synapses with CMOS neurons and learning circuits operating in the transistor subthreshold region to form a network of spiking neurons that can be utilized for pattern-recognition problems.

Figure 1

Neuron and synapse dynamics in response to a spike train.

Figure 2

Network connectivity utilized for pattern recognition. Neurons with lateral inhibitory connections receive input Poisson spike trains with an average rate proportional to the pixel intensity.

Figure 3

Device structure for a spintronic synapse with decoupled spike-transmission and programing-current paths. Spike current flows through the MTJ structure between terminals $T1$ and $T3$. Programing current flows through the HM between terminals $T2$ and $T3$.

Figure 4

Spintronic synapse with access transistors to decouple the programing- and spike-current paths.

Figure 5

Possible arrangement of synapses in an array interfaced with CMOS neurons and programing circuits. Shown are synapses connecting preneurons $A$ and $B$ to postneurons $C$ and $D$.

Figure 6

Subthreshold CMOS circuit utilized for generating the programing current involved in STDP learning (the circuit for the positive time window shown) for preneuron $A$, connecting to postneurons $C$ and $D$.

Figure 7

Detailed timing diagrams demonstrating the implementation of (a) potentiation (positive timing window) and (b) depression (negative timing window) in the spintronic synapse. POST is the control signal that is activated during programing, while PRE is the gate voltage of the $M_{\mathrm{STDP}}$ transistor that implements synaptic plasticity. Duration of the programing current is determined by the duration of the POST signal, while the magnitude is determined by the value of the PRE signal when the POST signal is high.

Figure 8

(a) DPI circuit interfaced with spintronic synapses to emulate synaptic dynamics. (b) Subthreshold CMOS neuron with leak conductance, spike-frequency adaptation, positive feedback, and refractory-period implementation blocks [28].

Figure 9

(a) Domain-wall displacement as a function of time for a CoFe strip of cross section $160\times 0.6\mathrm{nm}$ due to the application of a charge-current density, $J=0.1\times 10^{12}\mathrm{A}/{\mathrm{m}}^{-2}$. (b) Domain-wall velocity as a function of current density. The results are in good agreement with Ref. [21]. (c) Domain-wall displacement is directly proportional to the programing current for a fixed duration of the programing pulse.

Figure 10

The NEGF-based transport-simulation framework is calibrated to the experimental results illustrated in Refs. [36, 37]. MTJ resistance varies with (a) oxide thickness and (b) applied voltage.

Figure 11

(a) Linear variation of device conductance with domain-wall position. (b) Programing-circuit simulation to generate the STDP characteristics in the proposed spintronic synapse.

Figure 12

CMOS neuron response to a constant input current with positive feedback, spike-frequency adaptation, and refractory-period implementations.

Figure 13

(a) SNN topology used for digit recognition arranged in a crossbar array. (b) Initial random synapse weights plotted in a $28\times 28$ array for 100 neurons in the excitatory layer. (c) Representative digit patterns start getting stored in the synapse weights for each neuron after 1000 learning epochs.