Material Targets for Scaling All-Spin Logic

All-spin-logic devices are promising candidates to augment and complement beyond-CMOS integrated circuit computing due to nonvolatility, ultralow operating voltages, higher logical efficiency, and high density integration. However, the path to reach lower energy-delay product performance compared to CMOS transistors currently is not clear. We show that scaling and engineering the nanoscale magnetic materials and interfaces is the key to realizing spin-logic devices that can surpass the energy-delay performance of CMOS transistors. With validated stochastic nanomagnetic and vector spin-transport numerical models, we derive the target material and interface properties for the nanomagnets and channels. We identify promising directions for material engineering and discovery focusing on the systematic scaling of magnetic anisotropy ($H_k$) and saturation magnetization ($M_s$), the use of perpendicular magnetic anisotropy, and the interface spin-mixing conductance of the ferromagnet–spin-channel interface ($G_{\text{mix}}$). We provide systematic targets for scaling a spin-logic energy-delay product toward 2 aJ ns, comprehending the stochastic noise for nanomagnets.

Figure 1

(a) A lateral spin valve formed with two ferromagnetic layers with directional logic operation (inverting and noninverting gate). Spin channel (metal $A$) is formed of high spin-diffusion length material. The power supply and ground plane are formed with low resistivity material (metal $C$). (b) A stacking scheme for 3D all-metallic spin logic comprising of two layers of spin logic. Nonmagnetic vias allow for spin-current conduction out of plane creating a 3D stackable logic. A possible spin information flow out of plane is identified.

Figure 2

(a) Nominal operating condition of a spin-logic inverter (with a 10-mV supply voltage). (b) Electrical power injected into the device at the supply terminals is shown based on a vector spin circuit model. Nominal material properties are assumed for the baseline operation of the device. (c) Spin current along the $X$ direction (direction of channel length) injected at the magnets. (d) Equivalent spin circuit model for a lateral spin-logic device.

Figure 3

(a) Energy vs delay comparison of ASL devices with nominal materials using in-plane and PMA nanomagnets. (b) Perpendicular anisotropy nanomagnets. (c) Nanomagnet dynamics with in-plane magnetization.

Figure 4

(a) Effect of spin-diffusion length on the energy vs delay of an all-spin-logic device. (b) Effect of Gilbert damping on the energy vs delay of an all-spin-logic device.

Figure 5

(a) Energy vs delay comparison of in-plane ASL devices with nominal materials (red line) and scaled magnetic materials. An approximately linear order energy-delay improvement can be expected with higher $H_k$ and lower $M_s$. (b) Energy vs delay of PMA ASL, in-plane ASL, and improved PMA ASL (green curve) calculated via vector spin modeling of the ASL.

Figure 6

(a) FM-to-NM interface. (b) Four-component spin-mixing conductance of the interface. (c) Effect of spin-mixing conductance on energy vs delay of in-plane ASL devices with nominal materials (red line) and interfaces with enhanced spin-mixing conductance.

Figure 7

(a) Energy vs delay of nominal in-plane ASL, PMA ASL, scaled $H_k$ PMA ASL, and scaled PMA ASL with enhanced spin-mixing conductance. (b) Nanomagnet magnetic material and interface property targets for various projected devices.

Figure 8

Effective energy per cycle (J) including leakage power at 1-GHz clock rate. The 22-nm CMOS line assumes no active power management. The effect of nonlocal memory fetching and interconnects are not comprehended. Nonvolatile logic can provide effectively low energy per bit compared to CMOS at low activity factor utilization.