Designing Ferroelectric Field-Effect Transistors Based on the Polarization-Rotation Effect for Low Operating Voltage and Fast Switching

The effect of polarization rotation on the performance of metal-oxide-semiconductor field-effect transistors is investigated with a Landau-Ginzburg-Devonshire theory-based model. In this analytical model, the depolarization field, polarization rotations, and electrostatic properties of the doped silicon substrate are considered to illustrate the size effect of ferroelectric oxides and the stability of polarization in each direction. Based on this model, we provide guidance in designing electronic logic devices with low operating voltages and low active-energy consumption: First, we demonstrate that MOSFET operation could be achieved by polarization reorientation with a low operating voltage, if the thickness of the ferroelectric oxide is properly selected. Polarization reorientation can boost the surface potential of the silicon substrate, leading to a subthreshold swing $S$ lower than $60\mathrm{mV}/\mathrm{decade}$. We also demonstrate that, compared with polarization inversion, polarization rotation offers significant advantages, including a lower energy barrier and a wider range of transferability in nanoelectronic devices.

Figure 1

The schematic of a MOSFET with ferroelectric oxide as the insulator between the gate electrode and silicon substrate. The pink rectangles represent insulator layers isolating the side electrodes and source and drain terminals. (a) No gate voltage is applied ($V_g=0$), and the polarization is in plane. No carriers or current are in the channel. (b) Gate voltage is applied ($V_g>0$), and the polarization is out of plane. Carriers are induced by the polarization, and drain-source current flows.

Figure 2

Energy surfaces and their two-dimensional projections for MOSFET systems with ferroelectric oxide ${\text{BaTiO}}_3$ of different sizes. Parameters used in the simulation are given in Ref. [22]. (a) $d_x=400\mathrm{nm}$ and $d_z=200\mathrm{nm}$, polarization in plane favored. Polarizations corresponding to the four local minima are marked as $P_{x+}$, $P_{x-}$, $P_{z+}$, and $P_{z-}$. (b) $d_x=400\mathrm{nm}$ and $d_z=800\mathrm{nm}$, polarization out of plane favored. The polarization dynamics is marked with the dashed lines: path 1, polarization rotation; path 2, polarization inversion.

Figure 3

The relationship of the surface potential and interface charge density in the doped silicon substrate. Positive polarization (negative screening charge) corresponds to a larger surface potential and depolarization field.

Figure 4

The $P_{z+}$ versus $d_z$ plot. Only when the thickness in the $z$ direction $d_z$ is below 140 nm is $P_{z+}$ smaller than $0.223\mathrm{C}/{\mathrm{m}}^2$.

Figure 5

Hysteresis loop of the out-of-plane polarization $P_z$, with different values of ${\gamma }_0$.

Figure 6

(a) Hysteresis loop of the in-plane polarization $P_x$ and out-of-plane polarization $P_z$, effective polarization dynamic parameter ${\gamma }_0=1.0\times {10}^4\mathrm{m}/\mathrm{F}$. (b) $I_{\mathrm{ds}}-V_g$ curve of MOSFET. In the circled part, the inverse slope swing is lower than $60\mathrm{mV}/\mathrm{decade}$.

Figure 7

Potential diagrams of the systems with (a) polarization in the plane, so that in the $z$ direction the ferroelectric oxide is essentially a normal dielectric material; (b) polarization out of plane and both electrodes are noble metals; (c) polarization out of plane. The top electrode is noble metal, and the bottom one is doped silicon substrate. The potential should decay to 0. For simplicity, the curve truncates at 2 nm from the oxide-silicon interface.