Digital-Analog Quantum Simulation of Fermionic Models

Simulating quantum many-body systems is a highly demanding task since the required resources grow exponentially with the dimension of the system. In the case of fermionic systems, this is even harder since nonlocal interactions emerge due to the antisymmetric character of the fermionic wave function. Here, we introduce a digital-analog quantum algorithm to simulate a wide class of fermionic Hamiltonians including the paradigmatic one-dimensional Fermi-Hubbard model. These digital-analog methods allow quantum algorithms to run beyond digital versions via an efficient use of coherence time. Furthermore, we exemplify our techniques with a low-connected architecture for realistic digital-analog implementations of specific fermionic models.

Figure 1

The qubit Hamiltonian. The circles represent the qubits, each one labeled by a double index, the site in the lattice, and the orientation of the spin. The arrows linking the circles represent interactions. Each chain contains $n$ qubits, the number of considered sites. The top chain holds the up state of the fermion while the bottom one is employed to represent the fermionic down state. The one site energy is not shown.

Figure 2

The computation of $H_{ZZ}$. The top panel shows the graph representation of the mapping $H_I\to H_{ZZ}$, given in Eq. (7b), for three-site Fermi-Hubbard. The first graph on the left represents the Ising Hamiltonian $H_I$ given in Eq. (5) of the main text for the case $n_q=6$. The blue spheres are the vertices while the red lines represents the interaction between two linked vertices. Here $D_6$ is the operation that decouples the necessary interactions. Transformation $S_6=P_{3,4}{P}_{4,5}{P}_{2,3}$, represented by the two graphs in the shaded area of the figure, implements two sequences of swap gates, with a total of four swap layers, as indicated by the dashed arrows in the figures. Here $P_{i,j}$ means the permutation of sites $i$ and $j$. The result is the desired graph shown on the right, which represents the Hamiltonian $H_{ZZ}$. The bottom panel shows the quantum circuit of the process.

Figure 3

Qubit mappings onto a linear hardware. On top, the direct mapping of the qubits, and below, the “snakelike” mapping. We depict in red the physical linear device employed for the simulation. The numeric labels correspond to those employed in Eq. (4). With the direct mapping, the maximum distance between the two qubits representing the states up and down for the same fermion is equal to the number of fermions $n$. On the contrary, the snakelike mapping reduces this distance to 3 for any number of fermions.

Figure 4

The Trotterized evolution: digital quantum circuit for implementing the Trotterized evolution under the fermionic Hamiltonian. Note that the position of the qubits is the same at the start and at the end of each of the symmetric Trotter steps. We do not show here the SQGs to rotate the ${\sigma }^x{\sigma }^x$ and ${\sigma }^y{\sigma }^y$ interactions to the ${\sigma }^z{\sigma }^z$ axis.

Figure 5

The digital-analog schedule. (a) sDAQC schedule for the state preparation and the first term from the first Trotter step (see Fig. 4). See here that in order to simulate the evolution under the $H_{XX}^a$ Hamiltonian we need to apply a $Y^{\pm \pi /2}$ rotation to all qubits before and after the analog blocks. For this, we assume that our hardware only allows us to implement $x$ and $z$ rotations, so we employ the identity $Y^{\theta }=Z^{\pi /2}{X}^{\theta }{Z}^{-\pi /2}$. Employing the fact that single-qubit $z$ rotations commute with the evolution under the Ising Hamiltonian and by merging all the adjacent SQGs of the same type, we have simplified the circuit to what is shown in the figure. In blue we depict the hardware Ising Hamiltonian, in purple and green we depict the single-qubit $x$ and $z$ gates, respectively. In the sDAQC circuit, the interaction Hamiltonian is turned off during the application of the SQGs. The angles for the SQGs are shown inside the squares, while the time for the analog blocks is shown between them. (b) Corresponding bDAQC schedule. Note that since the Hamiltonian is always on, the length of the analog blocks is reduced to fit the SQGs while keeping the time in which the Hamiltonian is on, with $t_1^d=5/2t_x+2t_z$ and $t_2^d=3/2t_x+t_z$.

Figure 6

The ladder architecture. The blue circles represent the physical qubits, which interact with each other with strengths $\alpha$ and $\gamma$ with a $ZZ$ interaction. Given such ladder architecture, in order to implement the $H_{ZZ}$ Hamiltonian [Eq. (7b)] all we need to do is to decouple all the $\alpha$ interactions. This can be done by single-qubit rotations as explained in the text. To implement the $H_{XX}$ [Eqs. (7c) and (7d)] and $H_{YY}$ [Eqs. (7e) and (7f)] interactions, we need to decouple all the qubits linked by $\gamma$. This can also be done by single-qubit rotations. Moreover, by employing such single-qubit rotations, we can change the coupling between the desired qubits in order to achieve the target ones given by $ϵ$ and $\lambda$, in the same way we did in the examples discussed in the text.

Figure 7

Fidelity for the “snakelike” mapping. Fidelities for a different number of Trotter steps and times for the (a) stepwise and (b) banged DA circuits. The dotted lines represent the ideal implementation of the circuits, while the solid ones show the effect of the noise. Here we show the mean value over a maximum of 2000 runs with different initial random states. The fermionic Hamiltonian parameters are randomly set for each run with a uniform distribution in the ranges $ϵ=[1/2,2]$, $\mu =[1/4,1]$, and $\lambda =[1/2,2]$, while the hardware Hamiltonian is set at $\beta =1$. The time duration of the single-qubit gates are $t_{\mathrm{SQG}}={10}^{-3}$. The error parameters are $r_D=0.025$, $r_B^{\text{(sDAQC)}}=20$, $r_B^{\text{(bDAQC)}}={10}^{-4}$, $p_{\mathrm{bf}}={10}^{-4}$, $p_{\mathrm{th}}=0.35$, $T_1=100$, and $T_2=100$ (see Sec. 4a for definitions). All parameters are given in units of $\hslash =1$, and represent realistic parameters for the current NISQ era superconducting circuits [74].

Figure 8

Fidelity for the ladder architecture. Fidelities for a different number of Trotter steps and times for the (a) stepwise and (b) banged DA circuits. Here we employ $\alpha =\gamma =1$. The rest of the parameters are the same as in Fig. 7. In this architecture the digital analog can be implemented faster than in the nearest neighbor architecture. As a consequence, if we maintain the time for applying a SQG, the effect of the decoherence and the dephasing affect the outcome of the experiments less. This results in an improvement on the fidelity, especially for the bDAQC circuits.

Figure 9

The errors in measuring observables. (a) The difference between the expected value and the simulated measurements of the total density for the first site. In this plot we show the simulations of the noisy bDAQC circuits for the two topologies, with the same setup as in Fig. 7. As expected from the results of the fidelity, we obtain a more accurate measurement of the expected value of the observable for the case in which we employ the codesigned hardware. We note that there is an asymptotic behavior on the error of measuring the observables, close to the 0.2 mark, as seen for the “snake” topology and the codesigned experiment with $n_T=10$. Although not shown, the asymptotic behavior is also present for the on-site double-occupancy observable. (b) Measurements for the on-site double occupancy of the first site for different times and for the same initial state for the noisy bDAQC circuit in the codesigned hardware. In this case, we see that the simulation with $n_T=50$ yields a closer expected value to the exact one for times closer to $t=20$ than the simulation with $n_T=50$.