Gate-Tunable Transmon Using Selective-Area-Grown Superconductor-Semiconductor Hybrid Structures on Silicon

Albert Hertel, Michaela Eichinger, Laurits O. Andersen, David M.T. van Zanten, Sangeeth Kallatt, Pasquale Scarlino, Anders Kringhøj, José M. Chavez-Garcia, Geoffrey C. Gardner, Sergei Gronin, Michael J. Manfra, András Gyenis, Morten Kjaergaard, Charles M. Marcus, and Karl D. Petersson
Phys. Rev. Applied 18, 034042 – Published 16 September 2022

Abstract

We present a gate-voltage-tunable transmon qubit (gatemon) based on planar InAs nanowires that are selectively grown on a high-resistivity silicon substrate using III-V buffer layers. We show that low-loss superconducting resonators with an internal quality of 2×105 can readily be realized using these substrates after the removal of buffer layers. We demonstrate coherent control and readout of a gatemon device with a relaxation time, T1700ns, and dephasing times, T220ns and T2,echo1.3μs. Further, we infer a high junction transparency of 0.40.9 from an analysis of the qubit anharmonicity.

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  • Received 4 February 2022
  • Revised 18 February 2022
  • Accepted 30 June 2022

DOI:https://doi.org/10.1103/PhysRevApplied.18.034042

© 2022 American Physical Society

Physics Subject Headings (PhySH)

Condensed Matter, Materials & Applied PhysicsQuantum Information, Science & Technology

Authors & Affiliations

Albert Hertel1,*,‡,§, Michaela Eichinger1,‡, Laurits O. Andersen1, David M.T. van Zanten1, Sangeeth Kallatt1, Pasquale Scarlino2, Anders Kringhøj1, José M. Chavez-Garcia1, Geoffrey C. Gardner3,4, Sergei Gronin3,4, Michael J. Manfra3,4,5,6, András Gyenis1,¶, Morten Kjaergaard1, Charles M. Marcus1, and Karl D. Petersson1,2,†

  • 1Center for Quantum Devices, Niels Bohr Institute, University of Copenhagen, 2100 Copenhagen, Denmark
  • 2Microsoft Quantum Lab–Copenhagen, 2100 Copenhagen, Denmark
  • 3Birck Nanotechnology Center, Purdue University, West Lafayette, Indiana 47907, USA
  • 4Microsoft Quantum Lab–West Lafayette, West Lafayette, Indiana 47907, USA
  • 5Department of Physics and Astronomy, Purdue University, West Lafayette, Indiana 47907, USA
  • 6School of Materials Engineering, and School of Electrical and Computer Engineering, Purdue University, West Lafayette, Indiana 47907, USA

  • *a.hertel@fz-juelich.de
  • karl.petersson@microsoft.com
  • First two authors contributed equally.
  • §Current address: Institute for Semiconductor Nanoelectronics, Peter Grünberg Institute 9, Forschungszentrum Jülich & Jülich-Aachen Research Alliance (JARA), Forschungszentrum Jülich and RWTH Aachen University, Germany.
  • Current address: Department of Electrical, Computer & Energy Engineering, University of Colorado Boulder, CO 80309, USA.

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Vol. 18, Iss. 3 — September 2022

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