Specification format and a verification method of fault-tolerant quantum circuits

Quantum computations are expressed in general as quantum circuits, which are specified by ordered lists of quantum gates. The resulting specifications are used during the optimization and execution of the expressed computations. However, the specification format makes it difficult to verify that optimized or executed computations still conform to the initial gate list specifications: showing the computational equivalence between two quantum circuits expressed by different lists of quantum gates is exponentially complex in the worst case. In order to solve this issue, this work presents a derivation of the specification format tailored specifically for fault-tolerant quantum circuits. The circuits are considered a form consisting entirely of single qubit initializations, cnot gates, and single qubit measurements (ICM form). This format allows, under certain assumptions, to efficiently verify optimized (or implemented) computations. Two verification methods based on checking stabilizer circuit structures are presented.

Figure 1

A canonical topological circuit is constructed directly from a circuit level specification that is, in general, given in terms of the Clifford $+T$ library [1]. Our process assumes that the circuit level description has already been optimized and verified against a higher level specification and is therefore correct. The canonical topological circuit can be verified by inspection against the circuit description but is not optimized with respect to physical qubit and time resources due to its large 3D volume. Panel (a) represents a small state-distillation circuit containing eight qubits, five multitarget cnot gates, seven single qubits $S$ gates and seven Clifford measurements. The output of the circuit is the single uppermost qubit. Panel (b) is the canonical topological form. Each of the eight qubits are represented as pairs of white puzzle pieces or “defects” running left to right. Each cnot is a gray loop that braids with the relevant qubits in the circuit involved in the cnot, and the $S$ gates are the respective colored pyramid structures [1].

Figure 2

Representation of an ft circuit protected by the surface code [4]: (a) canonical; (b) optimized. Both circuits are functionally equivalent, and produce the same output, but circuit (b) requires far less physical resources (physical qubits, time) than circuit (a). Circuit (a) is easily mapped to the original circuit specification, while b) is not.

Figure 3

Circuits for performing a Hadamard gate using teleportation ancillae, cnot gates, and measurements. (a) Rotated initialization of ancillae; (b) rotated measurement of ancillae.

Figure 4

$P$-gate implementations: (b) rotated measurement (measure in Y basis); (c) rotated initialization (initialize in $Y$ basis). Transformations between implementations: (d) rewrite circuit (b) as (d); (e) replace the $P$ gate with circuit (c); (f) circuit (c) is transformed into (f). Increase measurement fidelity: (g) circuit (c) using a distillation procedure.

Figure 5

Fault-tolerant $T$-gate implementation. The measurement result of the top qubit determines the measurement basis on the other qubits: (a) rotated initialization [22]; (b) rotated measurement.

Figure 6

Circuit level verification example for the ICM $T$ gate: (a) original circuit used to derive the specification; (b) transformed circuit assumed to be existing in a black box.