Large-scale modular quantum-computer architecture with atomic memory and photonic interconnects

The practical construction of scalable quantum-computer hardware capable of executing nontrivial quantum algorithms will require the juxtaposition of different types of quantum systems. We analyze a modular ion trap quantum-computer architecture with a hierarchy of interactions that can scale to very large numbers of qubits. Local entangling quantum gates between qubit memories within a single register are accomplished using natural interactions between the qubits, and entanglement between separate registers is completed via a probabilistic photonic interface between qubits in different registers, even over large distances. We show that this architecture can be made fault tolerant, and demonstrate its viability for fault-tolerant execution of modest size quantum circuits.

Figure 1

Hierarchical modular quantum-computer architecture hosting $N=N_{\mathrm{ELU}}{N}_q$ qubits. (a) The elementary logic units (ELU) consist of a register of $N_q$ trapped atomic ion qubits, whereby entangling quantum logic gates are mediated through the local Coulomb interaction between qubits. (b) One or more atomic qubits within each of the $N_{\mathrm{ELU}}$ registers are coupled to photonic quantum channels, and through a reconfigurable optical crossconnect switch (OXC, center), fiber beamsplitters, and position sensitive imager (right), qubits between different registers can be entangled.

Figure 2

Elementary logic unit (ELU) composed of a single crystal of $N_q$ trapped atomic ion qubits coupled through their collective motion. (a) Classical laser fields impart qubit state-dependent forces on one or more ions, affecting entangling quantum gates between the memory qubits. Second ion species is introduced as refrigeration ions. (b) One or more of the ions (rightmost in the figure) are coupled to a photonic interface, where a classical laser pulse maps the state of these communication qubits onto the states of single photons (e.g., polarization or frequency), which then propagate along an optical fiber to be interfaced with other ELUs.

Figure 3

(a) Type I interference from photons emitted from two communication qubits. Each qubit is weakly excited so that single-photon emission has a very small probability yet is correlated with the final qubit state. The output photonic channels are mode matched with a 50:50 beamsplitter and subsequent detection of a photon from either output port heralds the entanglement of the communication qubits. The probability of two photons present in the system is much smaller than that of detecting a single photon. (b) Type II interference involves the emission of one photon from each communication qubit, where the internal state of the photon (e.g., its color) is correlated with the qubit state. After two-photon interference at the beamsplitter, coincidence detection of photons at the two detectors heralds the entanglement of the communication qubits.

Figure 4

Example of the MUSIQC and QLA hardware considered. (a) Each ELU in MUSIQC is made up of 100 physical qubits and six communication ports (only one shown in the figure), where 60 qubits are used to increase the bandwidth of the remote entanglement generation. These ELUs are connected through an OXC switch as shown in Fig. 1. (b) For QLA, each logic unit is made up of 49 physical qubits hosting four logical qubits and necessary ancilla qubits. (c) A logic block is six such logic units embedded in communication units. Communication units are square arrangements of $7\times 7$ qubits, and eight such units fully surround the logic unit.

Figure 5

(a) Execution time comparison of quantum ripple-carry adder (QRCA) on a nearest-neighbor architecture (green triangles), and quantum carry-lookahead adder (QCLA) on QLA (red squares) and MUSIQC (blue diamonds) architectures, as a function of the problem size $n$. All three circuits considered are implemented fault tolerantly, using one level of Steane [7,1,3] code. The execution time is measured in units of single-qubit gate time (SQGT), assumed to be $1\mu$s in our model. (b) Execution time (blue diamonds, left axis) and number of required physical qubits (red squares, right axis) of running fault-tolerant modular exponentiation circuit, representative of executing the Shor algorithm.

Figure 6

(a) Three steps of creating a 3D cluster state in the MUSIQC architecture, for fast entangling gates. (Step 1) Creation of Bell pairs between different ELUs, all in parallel. (Step 2) cnot gates (head of arrow, target qubit; tail of arrow, control qubit). (Step 3) Measuring of three out of four qubits per ELU. If the ELU represents a face (edge) qubit in the underlying lattice, the measurements are in the $Z$-($X$) basis. The resulting state is a 3D cluster state, up to Hadamard gates on the edge qubits. (b) Schedule for the creation of a 3D cluster state in the MUSIQC architecture. (Upper line) Schedule for Bell pair production between ELUs representing face and edge qubits. (Lower line) Schedule for the cnot gates within the ELUs corresponding to the front faces of the lattice cell. Schedules for the ELUs on other faces and on edges are similar.

Figure 7

Hypercell construction II. (a) Lattice cell of a three-dimensional four-valent cluster state. The dashed lines represent the edges of the elementary cell and the solid lines represent the edges of the connectivity graph. The three-dimensional cluster state is obtained by repeating this elementary cell in all three spatial directions. (b) Creating probabilistic links between several 3D cluster states. (c) Reduction of a 3D cluster state to a five-qubit graph state, via Pauli measurements. The shaded regions represent measurements of $Z$; the blank regions represent measurements of $X$. The qubits represented as black dots remain unmeasured. For details, see [71]. (d) Linking graph states by Bell measurements in the remaining ELUs. Four-valent, 3D cluster states of arbitrary size can be created.

Figure 8

Hypercell construction I. (a) Snowflake design of Refs. [74, 75]. (b) Connecting two hypercells. If the surface area is large, with high probability one or more Bell pairs are created between the surface areas via the photonic link. By Bell measurements within individual ELUs (indicated by ovals) one such Bell pair is teleported to the roots $A$ and $B$. (c) Boundary of the fault-tolerance region for gate error $\epsilon$ and ratio ${\tau }_E/{\tau }_D$, for various ELU sizes. The threshold for the gate error $\epsilon$ depends only weakly on ${\tau }_E/{\tau }_D$.

Figure 9

Circuit diagram for realizing fault-tolerant Toffoli gate using Steane code. (a) The initial state $|{\varphi }_{+}{\rangle }_L$ is prepared by measuring the $X_1$ and cnot${}_{12}$ of three-qubit state ${|0\rangle }_1{\left(\right|0\rangle }_2+{|1\rangle }_2{\left)\right|0\rangle }_3/\sqrt{2}$. Note that the Toffoli gate shown here is a bitwise Toffoli between the seven-qubit cat state and the two logical qubit states. (b) Using the state prepared in (a), the Toffoli gate can be realized using only measurement, Clifford group gates, and classical communication, all of which can be implemented fault tolerantly in the Steane code.