Robust hybrid qubit plane architecture for enhancing lattice-surgery-based surface codes

Quantum computing offers unprecedented speed and power for solving complex problems, but its susceptibility to errors makes error-correction codes crucial. An important metric for evaluating the performance of error-correction codes is the code distance, which measures the number of errors a code can correct. Current qubit-plane architectures are implemented using the same code distance. However, a larger code distance reduces the logical error rate but increases resources. In fact, distance-5 code uses more resources but offers higher resilience to logical errors compared to distance-3 code. We propose a qubit-plane architecture for rotated and unrotated surface codes called Qentaurus that combines various code distances of logical qubits for robust error correction while maintaining qubit efficiency. Qentaurus is designed to be highly scalable regarding computation, layout, and code distance. We performed a case study using Qentaurus with distance-3 and -7 codes to evaluate the performance. Moreover, we additionally developed a qubit placement scheme that considers the critical path of the quantum circuit to reduce the logical error rate and gate count. Our main experimental results demonstrated that Qentaurus considerably reduces the overall logical error rate (by 15.76% on average and up to 25.25%) than that of the Distance-3 Checkerboard architecture. After additionally implementing the qubit placement scheme, the average reduction increases to 13.44% (up to 39.07%). Notably, the Qentaurus-3&7 maintains logical error rates comparable to those of the Distance-5 Checkerboard, achieving considerable qubit efficiency. The Distance-5 Checkerboard demands 227.7% more physical qubits than that required by the Distance-3 Checkerboard, while Qentaurus-3&7 utilizes just 131.2% of the physical qubits required by Distance-3 the Checkerboard, marking a substantial reduction of 96.5% in the resource gap. The overall gate count is reduced by an average of 1.74% with Qentaurus alone and by 3.33% on average with the qubit placement scheme. We believe that the proposed Qentaurus and qubit placement scheme have the potential to significantly improve the error-correction performance of large-scale quantum computers in practical applications.

Figure 1

Examples of strong and weak logical qubits. The first left qubit (strong qubit) is a distance-7 code, and the right top and bottom qubits (weak qubits) are distance-3 code.

Figure 2

Qubit plane architectures. (a) Lattice surgery-based planar architecture [18], (b) checkerboard architecture [20], and (c) modified row-type architecture [33]. Brown patches hold logical data qubits, while white patches hold logical ancilla qubits.

Figure 3

Types of merge and split operations: (a) $2\times 2$ and (b) $3\times 3$ merge and split operations are represented using green circles.

Figure 4

Remote logical cnot operations between two distant qubits. (a) Control qubit is in patch 1, while the target qubit is in patch 3. (b) $Z$-boundary merging between patches 1 and 4 and $X$-boundary merging patches 3 and 5. (c) $Z$-boundary splitting between patches 1 and 4. (d) $Z$-boundary merging between patches 4 and 5. (e) Shrinking the merged qubit and reinitializing patches 4 and 5.

Figure 5

Case study demonstrating the utilization of magic state factories and data bus in Qentaurus. Magic-state factories distill high-quality magic states, which are essential for non-Clifford gate operations. The data bus (green logical qubits) efficiently delivers these high-quality magic states to the core of the Qentaurus layout.

Figure 6

Circuit diagram illustrating a single stabilization cycle during the error detection phase of QEC. Specific qubits undergo $Y$ rotations ($Y-$ and $Y+$), while controlled-phase (CZ) gates are applied to data and ancilla qubits. Gates are organized in color blocks for simultaneous application, with MZ representing $Z$ basis measurements. Dynamical decoupling (DD) is applied at the end of the data qubits to enhance error correction performance and mitigate decoherence effects.

Figure 7

Case study using distance-3 and distance-7 codes. (a) Topology view shows the physical qubits and stabilizers. (b) Layout view shows an abstract representation of the topology. The brown and white patches are logical data and ancilla qubits, respectively. (c) Connection view shows only logical data qubits and their connections, indicating logical cnot gates can be performed.

Figure 8

Qubit placement scheme: critical path analysis, qubit area analysis, and qubit arrangement. The resulting layout includes pairs of qubits in the circuit that correspond to logical qubits in the architecture.

Figure 9

Simulated surface-code logical error per cycle as a function of a scale factor $s$ on the error model [27]. Solid lines represent the fit experimental average of logical error rate per cycle for each code distance. $s=1.3$ is above the threshold where larger codes are worse, and $s<1.2$ is where the larger codes are better.

Figure 10

Relationship between logical cnot error rate and the scale factor of the error model. The investigated region includes the crossover regime ($s=0.6$ to 0.8) in which larger codes progressively improve until a turnaround occurs. The gap in scale factor $s$ within the crossover regimes aligns with the model previously presented in [27]. Larger codes improve in the region $s<0.6$ and worsen in the region $s>0.8$.

Figure 11

Tradeoff between the number of logical data qubits (LDQ) and physical qubits with different code distances.

Figure 12

Comparison of logical error rates of Checkerboards with distance-3 and distance-5 code, Qentaurus, and Qentaurus${}^{+}$. The results for the medium-sized circuits are magnified for clarity. ising: quantum simulation of ising model. qft: quantum Fourier transform. sqr: square root circuit.

Figure 13

Logical error rate of the sym9_195 circuit for Checkerboards, Qentaurus, and Qentaurus${}^{+}$. (a) Logical error rates on various architectures (data points are the logical error rates at each time point of the experiment). Panels (b), (c), and (d) display the logical error rates of physical qubits (left) and gate-density heatmaps (right) on the Checkerboard-5, Qentaurus, and Qentaurus${}^{+}$ architectures, respectively. For Qentaurus and Qentaurus${}^{+}$, qubits with indices 8, 9, 13, and 23 are considered as strong qubits with a distance-7 code; all others are weak qubits with a distance-3 code.

Figure 14

Comparision of the depth of Checkerboards with those of distance-3 and distance-5 codes, Qentaurus, and Qentaurus${}^{+}$. The magnified view shows medium-sized circuits, while large-sized circuits are shown at normal sizes.

Figure 15

Scalability of the proposed architecture regarding (a) size and (b) both size and code distance.