Optimizing quantum algorithms on bipotent architectures

Vigorous optimization of quantum gates has led to bipotent quantum architectures, where the optimized gates are available for some qubits but not for others. However, such gate-level improvements limit the application of user-side pulse-level optimizations, which have proven effective for quantum circuits with a high level of regularity, such as the ansatz circuit of the quantum approximate optimization algorithm (QAOA). In this paper, we investigate the trade-off between hardware-level and algorithm-level improvements on bipotent quantum architectures. Our results for various QAOA instances on two quantum computers offered by IBM indicate that the benefits of pulse-level optimizations currently outweigh the improvements due to vigorously optimized monolithic gates. Furthermore, our data indicate that the fidelity of circuit primitives is not always the best indicator for the overall algorithm performance; their gate type and schedule duration should also be taken into account. This effect is particularly pronounced for QAOA on dense portfolio optimization problems, since their transpilation requires many swap gates, for which efficient pulse-level optimization exists. Our findings provide practical guidance on optimal qubit selection on bipotent quantum architectures and suggest the need for improvements of those architectures, ultimately making pulse-level optimization available for all gate types.

Figure 1

Bipotent architecture of ibmq_ehningen. It contains two types of cx gates: direct-cx, represented by blue or dark gray edges, and ecr-cx, represented by orange or medium gray edges. Qubits are depicted as circles, and the lines between the qubits are connections where a cx gate can be applied. When only one type of cx gate can be applied, the qubit has the same color as the cx gate type, otherwise it is green (light gray).

Figure 2

Different implementations of cx and zz gates on IBM's QPUs. (a) Symbol of cx gate. (b) direct-cx gate on qubits [1, 4]. (c) ecr-cx gate on qubits [1, 0]. (d) Hardware implementation of the ecr-cx gate. (e) Decomposition of zz gate. zz gate implemented by (g) direct-cx gates on qubits [1, 4] and (f) ecr-cx gates on qubits [1, 0]. (h) ${\mathrm{ZZ}}_{\mathrm{OPT}}$ gate, the pulse-level optimization of (f).

Figure 3

Schedules of (a) direct-cx on qubits [1, 4] and (b) ecr-cx on qubits [1, 0].

Figure 4

Properties of ecr-cx (orange, medium gray) and direct-cx (blue, dark gray) gates on ibmq_ehningen. (a) Gate error rate. (b) Execution time in nanoseconds.

Figure 5

Properties of 27 qubits on ibmq_ehningen used for experiments in this article. (a) $T_1$ and (b) $T_2$ decoherence times. A higher value is better. (c) Single-qubit gate error and (d) readout error. A lower value is better. We label qubits connected to two types of cx gates as Q-bipotent (green, light gray) and qubits connected only to ecr-cx or direct-cx gates as Q-ECR (orange, medium gray) or Q-direct (blue, dark gray), respectively.

Figure 6

Pretranspiled circuit of QAOA for PortOpt with five qubits and $p=1$ on a linear topology [33]. For higher $p$, the circuit between the initial state and measurement is repeated $p$ times, each time with new parameters.

Figure 7

Different implementations (up to a global phase) of cz and zz-swap gates on IBM's QPUs. (a) Decomposition of cz gate. cz gate implemented by (b) direct-cx gate on qubits [1, 4] and (c) ecr-cx gate on qubits [1, 0]. (d) ${\mathrm{CZ}}_{\mathrm{OPT}}$ gate, the pulse-level optimization of (c). (e) Decomposition of zz-swap gate. (f) Alternative decomposition of the zz-swap gate into cz gates. (g) ${\mathrm{ZZ}-\mathrm{SWAP}}_{\mathrm{OPT}}$ gate, the implementation of (f) on qubits [1, 0] using ecr-cx gates with pulse-level optimization

Figure 8

Infidelity determined by QPT on the ibmq_ehningen. For (a), the zz gate acts on qubits [5, 8] with a gate repetition of 1 (left) and [1, 0] with a gate repetition of 10 (right). For (b), the zz-swap gate acts on qubits [1, 0] with a repeated number of gates of 10 (left) and 20 (right).

Figure 9

QAOA circuits. ECR, direct, and global circuits consider fidelity and restrict the cx gate type in the circuit to only ecr-cx, only direct-cx, and regardless of its type, respectively, whereas Bipotent-circuits have a trade-off between fidelity, schedule duration, and gate type.

Figure 10

Approximation ratio, success probability, schedule duration, and cx gate count of QAOA for PortOpt with $p$ from 1 to 5 using ECR, global, and direct circuits on ibmq_ehningen for (a) 3Q, (b) 4Q, and (c) 5Q. The average cx gate error rates are $0.48\%$ in all global circuits, they are $0.78\%, 0.87\%$, and $0.89\%$ in ECR circuits for 3Q, 4Q, and 5Q, respectively, while $0.48\%$ and $0.60\%$ in direct circuits for 4Q and 5Q, respectively.

Figure 11

Benchmarking results of QAOA for PortOpt using bipotent and global circuits on ibmq_ehningen for (a) 3Q and (b) 5Q, and (c) on ibm_auckland for 5Q. The average cx gate error rates for each data point in (a), (b), and (c) are 0.60%, 0.65%, and 0.67%, respectively.

Figure 12

Bipotent architecture of ibm_auckland. It has the same label as ibmq_ehningen.

Figure 13

Benchmarking results of 5Q-QAOA for MaxCut on ibmq_ehningen using two sets of circuits: (a) ECR, global, and direct circuits, and (b) bipotent and global circuits. The average cx gate error rates in the ECR circuits, Global-B, and direct circuit are 0.89%, 0.48%, and 0.60%, respectively, while that of each data point in (b) is 0.48%.