Gate-set tomography of fermionic systems using Majorana-fermion operations

Quantum tomography is an important tool for the characterization of quantum operations. In this paper we present a framework of quantum tomography in fermionic systems. Compared with qubit systems, fermions obey the superselection rule, which sets constraints on states, processes, and measurements in a fermionic system. As a result, we can only partly reconstruct an operation that acts on a subset of fermion modes and the full reconstruction always requires at least one ancillary fermion mode in addition to the subset. We also report a protocol for the full reconstruction based on gates in a Majorana-fermion quantum computer, including a set of circuits for realizing the informationally complete state preparation and measurement.

Figure 1

Circuits for the quantum process tomography of Majorana-fermion modes: (a) To measure the process $\mathcal{M}$ on $2m$ Majorana-fermion modes $c_1,c_2,...,c_{2m}$, we need a pair of ancillary modes $c_{2m+1}$ and $c_{2m+2}$. Majorana fermions are initialized in a pairwise manner in the eigenstate of $i{c}_{2i-1}{c}_{2i}$ with the eigenvalue $+1$, where $i=1,2,...,m+1$. Gates $G,G^{\prime }\in {\mathbf{G}}_{m+1}$ that act on the $2m+2$ modes are generated according to (b) and (c). After the gate $G$, the process $\mathcal{M}$ is implemented on the first $2m$ modes. Following the process $\mathcal{M}$, the gate $U=G^{\prime -1}$ is performed. Then the final state is measured in a pairwise manner, i.e., the eigenvalue of each $i{c}_{2i-1}{c}_{2i}$ is the measurement outcome. (b) Circuit for generating ${\mathbf{G}}_{m+1}$ (see Sec. 6a). The inverse of the circuit generates ${\mathbf{U}}_{m+1}$ (see Sec. 6b). Here $G_k$ is a $2k$-mode gate. To generate a $(2k+2)$-mode gate, the $S$ gate is performed on modes $c_{2k-1}$, $c_{2k}$, $c_{2k+1}$, and $c_{2k+2}$. To generate a gate $G$ for the state preparation, we take $S=S_0,S_1,S_2,S_3$. To generate a gate $G^{\prime }$ for the measurement, we take $S=S_0,S_1,S_2$. (c) Circuits built on exchanges gates. Here $S_0=\mathbb{1}$, $S_1=R_{c_{2k},c_{2k+1}}$, $S_2=R_{c_{2k},c_{2k+2}}$, and $S_3=R_{c_{2k},c_{2k+1}}^2$.