Scalable quantum computing with qudits on a graph

We show a significant reduction of the number of quantum operations and the improvement of the circuit depth for the realization of the Toffoli gate by using qudits. This is done by establishing a general relation between the dimensionality of qudits and their topology of connections for a scalable multiqudit processor, where higher qudit levels are used for substituting ancillas. The suggested model is of importance for the realization of quantum algorithms and as a method of quantum error correction codes for single-qubit operations.

Figure 1

Illustration of various multiqudit and qubit-qudit schemes for quantum computing that provides reduction in the number of operations for the realization of the Toffoli gate and reduces the depth of the corresponding circuit. We note that if condition (3) holds for a whole system, then it is also fulfilled for any of its acyclic-connected subsystem (highlighted).

Figure 2

In (a) we present the decomposition of $N$-qubit Toffoli gate C${}^{N-1}X{}^{\left(t\right)}$ in C${}^{N-1}Z$ and Hadamard gates. In (b) an example of the connection topology of an eight-qudit system is shown. Here $\tilde{E}\subset E$ is a subset of connections, which correspond to the connected acyclic graph. Numbers in the nodes correspond to minimal dimensions of qudits determined by the general condition (3). In (c) the action of three general steps in the tree representation is presented. The first step is the folding operation, which wraps the original tree to the single-level form. The second step is the basic operation, which does not change the tree. The third step is the unfolding operation that returns the tree to its original form. In (d) the elementary folding operation with the corresponding circuit is shown. In (e) the circuit corresponding to the basic operation for the C${}^{N-1}Z$ gate is presented.

Figure 3

In (a) the decomposition of C${}^{N-1}U{}^{\left(k\right)}$ operation using the spectral decomposition of $U$ is shown. In (b) the C${}^N\mathbf{U}{}^{(R_1,...,R_M)}$ gate is shown. In (c) the circuit corresponding to the basic operation for the C${}^N\mathbf{U}$ gate is shown.