Looped Pipelines Enabling Effective 3D Qubit Lattices in a Strictly 2D Device

Many quantum computing platforms are based on a two-dimensional (2D) physical layout. Here we explore a concept called looped pipelines, which permits one to obtain many of the advantages of a three-dimensional (3D) lattice while operating a strictly 2D device. The concept leverages qubit shuttling, a well-established feature in platforms like semiconductor spin qubits and trapped-ion qubits. The looped-pipeline architecture has similar hardware requirements to other shuttling approaches, but can process a stack of qubit arrays instead of just one. Even a stack of limited height is enabling for diverse schemes ranging from NISQ-era error mitigation through to fault-tolerant codes. For the former, protocols involving multiple states can be implemented with a space-time resource cost comparable to preparing one noisy copy. For the latter, one can realize a far broader variety of code structures; as an example we consider layered 2D codes within which transversal cnots are available. Under reasonable assumptions this approach can reduce the space-time cost of magic state distillation by 2 orders of magnitude. Numerical modeling using experimentally motivated noise models verifies that the architecture provides this benefit without significant reduction to the code’s threshold.

Popular Summary

The key challenge in building useful quantum computers is to tackle “noise”—the tendency of the computer's internal state to degrade because of unwanted or imperfect interactions. Solutions are known, such as quantum error correction in the long term and error mitigation for near-future machines. But these come at high cost, requiring many times more qubits and/or a much longer run-time than would be needed in the absence of noise. This paper shows how it is possible to greatly reduce these costs. The method applies to types of quantum hardware where qubits interact at short range but can be physically “shuttled” from place to place. Several promising approaches of this type exist, including systems involving electron spins in semiconductors and also certain kinds of ion-trap devices.

Shuttling is a natural solution for moving qubits around a 2D array so that they can interact wherever required. We show that by changing from previously studied linear shuttling paths to shuttling orbits and by adopting the concept of pipelining from classical computing, the resulting looped-pipeline architecture can act as if there were a finite third dimension to the array. We can then process an entire stack of logical qubits in each 2D region. This allows for higher qubit density and more efficient logical gates utilizing transversal operations. Meanwhile for devices employing error mitigation rather than correction, our architecture greatly reduces the cost of virtual distillation, which is one of the most powerful such schemes.

In general, our architecture is a way to attain many of the advantages of a 3D lattice while operating a strictly 2D device. It will be interesting to look at other ways to make use of this newfound 3D connectivity, for example, a more practical implementation of 3D codes or algorithms with a natural 3D embodiment.

Figure 1

Example of a classical data pipeline consists of $4$ steps. Here we have a steady flow of datasets with a time gap ${\tau }_{\max }$ between consecutive datasets.

Figure 2

Pipelines for applying single-qubit circuits on a stream of qubits.

Figure 3

Example of a looped qubit pipeline with multiple initialization or measurement devices.

Figure 4

Five-qubit arrays stored in a loop array. Multiple qubits can be stored on the same loop through pipelining, which corresponds to multiple layers of five-qubit arrays.

Figure 5

(a) An entire array of loops, sufficient for a given role (a NISQ calculation, or representing one logical qubit) may be only part of the entire device. (b) Transforming a given qubit connectivity graph to a pipelining architecture. The shuttling loop of a given qubit is simply constructed by connecting up the midpoints of all of its interaction edges.

Figure 6

Interactions within layers are enabled by interloop (red) interactions while transversal interaction in between layers are enabled by intraloop (green) interactions.

Figure 7

Constructing 3D qubit connectivity without using intraloop interactions. Here the cycling frequency of the center (gray) loop is twice as fast as that of the surrounding (white) loops. Interactions between the middle two layers can be enabled if we allow qubit swaps within the same loops as shown in Fig. 8.

Figure 8

A qubit pipelining scheme to achieve the qubit connectivity shown on the left using loops of different cycling frequencies and a different number of qubits. Here the only intraloop operation we need is swapping the qubits in the same loop, which can be carried out using swap gates or via qubit shuttling if we allow one qubit to bypass another qubit in the loop. Qubit bypass in the loop can be achieved by adding structures to allow one qubit to move off the loop to give way to another qubit.

Figure 9

One possible way to implement the interactions between two loops using shuttling junctions.

Figure 10

Edge-interacting qubit-array pipelines. Intraloop gate devices are not explicitly shown for visual clarity. We see that multiple qubit pairs can interact simultaneously along a given edge.

Figure 11

The surface code and its parity-check circuits.

Figure 12

Pipelining architecture for surface codes. Intraloop gate devices are not explicitly shown for visual clarity. The initialize or readout devices on the data qubit tracks are not used during a normal stabilizer cycle. More specialized hardware design with heterogeneous data and ancilla loops is possible, but is not shown here for simplicity. Note that here all data and ancilla pipelines are flowing in the clockwise direction. It is also possible to run in a configuration that all data pipelines flow clockwise while all ancilla pipeline flow anticlockwise.

Figure 13

Pipeline workflow for a code cycle in surface codes. “Shuttle” here means shuttling along one edge of the square shuttling loop. “Wait” here means buffering and it needs to be added into the pipeline for synchronization depending on which pipeline is the rate-limiting pipeline. We do not include the initializations of qubits before all code cycles and the measurement of all qubits after all code cycles.

Figure 14

A logical qubit in the color code.

Figure 15

Pipelining architecture for color-code parity checks with six qubits in the pipeline. Intraloop gate devices are not explicitly shown for visual clarity. Here we effectively have six layers of parity-check units stacking on top of each other.

Figure 16

A possible layout for storing logical information in multiple stacks. Here each square is an array of loops that can store a stack of logical qubits. The ancilla logical qubits (stacks) do not need to be always present and thus are not explicitly shown here.

Figure 17

Illustration of how cnots can fail to be parallelized when using lattice surgery (a), when using a simple 2D architecture. Here we are trying to perform cnots using lattice surgery between the two blue qubits and the two purple qubits. They cannot be carried out in parallel because they both need to make use of the center ancilla patch. In (b), we see this is possible with the virtual stack.

Figure 18

Gate teleportation circuit for implementing $T$ gate. The $S$ gate ($S=e^{-i\pi /4Z}$) is only applied when we obtain the $1$ outcome from the $Z$ measurement. If we change the correction to applying an $S^{†}$ gate when we obtain the $0$ outcome from the $Z$ measurement, we would be implementing $T^{†}|\psi ⟩$ instead.

Figure 19

Circuit to perform $15$-to-$1$ magic state distillation from Ref. [34]. It starts with preparing the logical state of the distillation code $|\overline{0}⟩$, then we prepare a Bell state between this logical qubit and the ancilla qubit $\propto |\overline{0}0⟩+|\overline{1}1⟩=|\overline{+}+⟩+|\overline{-}-⟩$. After that we implement the transversal $T$ gates by consuming noisy $|T⟩$ using the circuit in Fig. 18. Note this requires an additional qubit at each location marked $T^{†}$ in the figure, 15 in total, implying 31 qubits to execute the circuit. All qubits above are encoded in the base code (none are simply “physical” qubits). At the end, we perform local $X$ measurements to obtain the $X$ stabilizer checks and logical $X$ measurement of the distillation code. Any circuit runs with failed $X$ stabilizer checks are discarded.

Figure 20

Circuit to perform $15$-to-$1$ magic state distillation with fewer qubits but a deeper circuit from Ref. [51]. In this case, the $15$ noisy $|T⟩$ are not consumed in parallel, but in three rounds. In other words, we need only to consume $5|T⟩$ at one time. Thus we can use five qubits for the distillation code and five qubits for generating the noisy $|T⟩$. For the measurement at the end, we are only postselecting the circuit runs that measure $|+⟩$ for the first four qubits. The circuit here can be further optimized by removing some of the cnot gates at the end that acts trivially on the postselected states of the first four qubits ${|+⟩}^{\otimes 4}$, and by recompiling the cnot gates in between different rounds of $T$ gates. Note that all qubits above are encoded in the base code.

Figure 21

Diagram showing the different error locations in the $X$-check circuits in our error model.

Figure 22

Threshold plots for the dephasing errors ($p_{\mathrm{sh}}$), leakage errors ($p_{\mathrm{leak}}$), and the Rashba error ($p_{\mathrm{rash}}$) due to shuttling when implementing surface codes in semiconductor spin qubit using shuttling-based architectures. Note that in order to investigate the tolerance of the surface code against a given specific type of shuttling noise, the other types shuttling noise are turned off in our simulation. Each noise type is evaluated both for a gate error rate $p$ of zero, and for $p=0.5\mathrm{\%}$.

Figure 23

Diagram showing the different error locations in the $X$-check circuits with the shuttling errors coming from Rashba interaction.

Figure 24

Measurement circuit in each loop for purification-based QEM.

Figure 25

Pipeline workflow for a code cycle in color code. As illustrated in the diagram, “Wait” needs to be added into the pipeline for synchronization depending on which pipeline is the rate-limiting pipeline. We do not include the initializations of qubits before all code cycles and the measurement of all qubits after all code cycles.

Figure 26

Diagram showing the change of the time gap of the qubit stream as it passes through different steps in the pipeline.