Abstract
In order to treat all-to-all-connected quadratic binary optimization problems (QUBOs) with hardware quantum annealers, an embedding of the original problem is required due to the sparsity of the topology of the hardware. The embedding of fully connected graphs—typically found in industrial applications—incurs a quadratic space overhead and thus a significant overhead in the time to solution. Here, we investigate this embedding penalty of established planar embedding schemes such as square-lattice embedding, embedding on a chimera lattice, and the Lechner-Hauke-Zoller scheme, using simulated quantum annealing on classical hardware. Large-scale quantum Monte Carlo simulation suggests a polynomial time-to-solution overhead. Our results demonstrate that standard analog quantum annealing hardware is at a disadvantage in comparison to classical digital annealers, as well as gate-model quantum annealers, and could also serve as a benchmark for improvements of the standard quantum annealing protocol.
3 More- Received 29 March 2021
- Revised 13 August 2021
- Accepted 8 September 2021
DOI:https://doi.org/10.1103/PRXQuantum.2.040322
Published by the American Physical Society under the terms of the Creative Commons Attribution 4.0 International license. Further distribution of this work must maintain attribution to the author(s) and the published article's title, journal citation, and DOI.
Published by the American Physical Society
Physics Subject Headings (PhySH)
Popular Summary
Adiabatic quantum optimization has the potential to revolutionize several fields of research, as well as industrial optimization. However, many real-world optimization problems require an all-to-all graph topology. For example, any optimization problem with constraints that might be on a sparse graph becomes an all-to-all optimization problem when cast as a quadratic binary optimization problem for a quantum annealer. To accommodate an all-to-all topology, the problem has to be embedded into the hardwired topology of currently available quantum annealing hardware. A typical example is the traveling-salesperson problem: not only is there a quadratic overhead in the number of variables when enforcing a closed-loop topology but there is an additional quadratic overhead when embedding the tour in a sparse-graph quantum annealer. While this in itself can be discouraging, here we demonstrate that commonly used embedding schemes not only incur a space overhead but also a significant overhead in the time to solution.
Using large-scale quantum Monte Carlo simulations, we demonstrate that standard analog quantum annealing hardware is at a disadvantage in comparison to classical digital annealers, as well as gate-model quantum annealers that can easily accommodate an all-to-all topology. Our work highlights the need to develop new hardware paradigms that overcome the fundamental challenges found in current devices.