Machine Learning of Noise-Resilient Quantum Circuits

Noise mitigation and reduction will be crucial for obtaining useful answers from near-term quantum computers. In this work, we present a general framework based on machine learning for reducing the impact of quantum hardware noise on quantum circuits. Our method, called noise-aware circuit learning (NACL), applies to circuits designed to compute a unitary transformation, prepare a set of quantum states, or estimate an observable of a many-qubit state. Given a task and a device model that captures information about the noise and connectivity of qubits in a device, NACL outputs an optimized circuit to accomplish this task in the presence of noise. It does so by minimizing a task-specific cost function over circuit depths and circuit structures. To demonstrate NACL, we construct circuits resilient to a fine-grained noise model derived from gate set tomography on a superconducting-circuit quantum device, for applications including quantum state overlap, quantum Fourier transform, and $W$-state preparation.

Popular Summary

The rise of quantum computing over the past few years is incredibly exciting. In the near future, quantum computers may be large enough to outperform classical computers for practically interesting problems like simulating chemistry. But everyone agrees that this will not be possible without intense effort to reduce the impacts of noise on quantum circuits. A central open question is, therefore, how to design quantum circuits that minimize the accumulation of noise.

There is a recent history of machines outperforming humans at various tasks, including games (like Chess, Go, Jeopardy) and even tasks that humans have evolved to excel at (like facial recognition). Now imagine a task for which humans have essentially zero intuition: designing quantum circuits. Let us make the task even more complicated by having a device-specific noise process, so that the goal is to design a circuit that runs well on a given quantum computing hardware. Is there any doubt that a machine could perform this task better than a human?

In this work, we develop a framework to leverage the incredible advances in the field of machine learning for the purpose of designing noise-resilient quantum circuits. We train our circuits in the presence of a noise model for a specific device, so that the circuit evolves to be immune to the noise on that device. This is analogous to taking a vaccine, to become immune to a virus. Indeed, with our new framework, we demonstrate significant reductions in the computational error for key computational tasks under experimentally derived error models for superconducting-qubit quantum computers.

Figure 1

Applications of NACL. (a) In compiling, the goal is to approximate an input unitary matrix $U$ by a noise-resilient circuit that is compatible with the device constraints. (b) In state preparation, one inputs a set of $N$ input and output states $\{|x_i⟩,|y_i⟩\}$, where $N$ could be as small as 1, and the output is a noise-resilient circuit that approximately prepares the $|y_i⟩$ states from the $|x_i⟩$ states. (c) In observable extraction, one inputs a set of input states and classical outputs that typically correspond to local observable expectation values, $\{|x_i⟩,y_i\}$, and the output is a noise-resilient circuit that approximately computes the outputs from any input state $|\psi ⟩$ that might or might not be in the input set.

Figure 2

Schematic diagram of NACL. Our approach takes a task and a device model as an input. The task is defined via examples in a training set and a cost function, $C$. That information is sufficient to find a noise-aware circuit that approximates a specified task. It is done via optimization over a set of parameters $(L,\overrightarrow{k},\overrightarrow{\theta })$ that describe a quantum circuit. The algorithm returns parameters $(L_{\mathrm{opt}},{\overrightarrow{k}}_{\mathrm{opt}},{\overrightarrow{\theta }}_{\mathrm{opt}})$, which represent an optimized quantum circuit that minimizes the cost function $C$. See the text for details.

Figure 3

Qubit layout and connectivity for device modeled in the noise model used to demonstrate NACL. This layout is inspired by the IBM Q Ourense device, and the lines indicate the qubits that can participate in cnot coupling gates.

Figure 4

The textbook swap test–based circuit for state overlap estimation when the input states ($\rho$, $\sigma$) are single-qubit states. It is obtained by decomposing the swap operation into a standard universal gate set.

Figure 5

The form of the textbook swap test–based overlap estimation circuit, shown in Fig. 4, when decomposed into the native gates in our device model. Here $P$ denotes the pulse gate, or $X(\pi /2)$ rotation, and $I$ is an idle timestep. The vertical lines denote $Z(\theta )$ rotations that are done virtually and therefore take no time. This notation helps with visualizing which gates can be performed in parallel. Values of ${\theta }_n$ are shown in Appendix pp1.

Figure 6

(a) Machine learned circuit found without considering the noise model. (b) The circuit decomposed into the native gates in the device model. The notation is the same as in Fig. 5. Values of ${\theta }_n$ are shown in Appendix pp1.

Figure 7

Machine learned circuit found by NACL incorporating the noise model. The notation is the same as in Fig. 5. Values of ${\theta }_n$ are shown in Appendix pp1.

Figure 8

(a) A comparison of the error in computing state overlap [as quantified by Eq. (18)] for each of the validation samples for the three circuits: textbook (${\mathcal{A}}_1$, blue), noise unaware ML (${\mathcal{A}}_2$, red), and NACL (${\mathcal{A}}_3$, green). The $x$-axis indexes pairs of states in the validation data set. The inset shows differences in error. (b) Overlap estimation error for the three circuits as a function of the exact value of the overlap $\mathrm{Tr}({\rho }_j{\sigma }_j)$. The inset shows a histogram of exact overlaps for the validation data set.

Figure 9

(a) Textbook circuit for preparing $|W_4⟩$. (b) Decomposition of a control-$G(p)$ gate into cnot and one-qubit gates $u$ and $u^{†}$, where $u=e^{-iY\alpha }$ and $\alpha =\arcsin (\sqrt{p})/2$. (c) Compilation of the textbook circuit shown in (a) into the first four qubits of the device model in Fig. 3. The notation is the same as in Fig. 5. The values of angles ${\theta }_j$ are given in Appendix pp1.

Figure 10

Circuit that prepares $|W_4⟩$ found by NACL. The notation is the same as in Fig. 5. Angles ${\theta }_j$ are specified in Appendix pp1.

Figure 11

(a) Circuit for preparing $|W_5⟩$ obtained by following the construction given in Ref. [35]. The first controlled-$G(p)$ gate can be simplified, as the first qubit is initialized in $|1⟩$. This allows for a shorter compilation. (b) Its best compiled version achieved by a proper permutation of qubits. The notation is the same as in Fig. 5. Angles ${\theta }_j$ are given in Appendix pp1.

Figure 12

The circuit that approximates preparation of $|W_5⟩$ found by NACL. The notation is the same as in Fig. 5. Angles ${\theta }_j$ are given in Appendix pp1.

Figure 13

(a) A textbook circuit for performing QFT on three qubits. (b) A compilation of the circuit in (a) into the native gate set in the device model we are simulating. The compilation has to take into account the fact that qubits 1 and 3 are not directly connected. Angles ${\theta }_j$ are specified in Appendix pp1.

Figure 14

Circuit performing QFT found by NACL. The notation is the same as in Fig. 5. Angles ${\theta }_j$ are given in Appendix pp1.

Figure 15

Performance of textbook, qsearch-generated, and NACL-generated circuits to evaluate QFT. The figure shows error (as defined in the text) for 1000 randomly generated pure states. The NACL-generated circuit performs much better than the textbook one on all considered states. The circuit found by NACL also has a lower error than that generated by qsearch.

Figure 16

NACL performance. Panels show compilation quality as a function of the wall-clock time. The definition of compilation quality depends on a particular task; see the text for details. Panels (a)–(d) show NACL performance as applied to observable extraction, three-qubit QFT compilation, and four-qubit and five-qubit $W$-state preparation, respectively.