Electronic Transport in Hydrogen-Terminated Si(001) Nanomembranes

Weina Peng, Marziyeh Zamiri, Shelley A. Scott, Francesca Cavallo, James J. Endres, Irena Knezevic, Mark A. Eriksson, and Max G. Lagally

Phys. Rev. Applied 9, 024037 – Published 28 February 2018

Abstract

Charge carrier transport in thin hydrogen (H)-terminated Si(001) sheets is explored via a four-probe device fabricated on silicon-on-insulator (SOI) using the bulk host Si as a back gate. The method enables electrical measurements without the need to contact the sample surface proper. Sheet conductance measurements as a function of back-gate voltage demonstrate the presence of acceptor- and donorlike surface states. These states are distributed throughout the gap and can be removed or transformed with low-temperature annealing. The density of donorlike states is just under $10^{12} {cm}^{- 2} {eV}^{- 1}$ and 3 times higher than that of the acceptorlike states. We discuss the possible origins of these states. The conductance through the surface layer is too small to measure.

Received 17 August 2017
Revised 6 November 2017

DOI:https://doi.org/10.1103/PhysRevApplied.9.024037

Physics Subject Headings (PhySH)

Electrical conductivity Electrical properties Semiconductors Surface states

2-dimensional systems Devices Ultrathin films

Resistivity measurements

Condensed Matter, Materials & Applied Physics

Authors & Affiliations

Weina Peng^1,†, Marziyeh Zamiri^1,*, Shelley A. Scott¹, Francesca Cavallo², James J. Endres¹, Irena Knezevic¹, Mark A. Eriksson¹, and Max G. Lagally¹

¹University of Wisconsin-Madison, Madison, Wisconsin 53706, USA
²Department of Electrical and Computer Engineering, Center for High Technology Materials, University of New Mexico, Albuquerque, New Mexico 87106, USA

^*Corresponding author. szamiri@wisc.edu
^†Present address: Micron Technology, 8000 South Federal Way, Boise, Idaho 83716, USA.

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Vol. 9, Iss. 2 — February 2018

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Images

Figure 1
Schematic diagram of the van der Pauw measurement on Si NMs and a cross section of the device. (a) A mesa is patterned on the SOI wafer representing an inverted MOSFET structure. The central region is $4 \times 4 {mm}^{2}$ ; the four corner contacts are doped with P. One of eight possible measurements is shown in the diagram, with current passing through two adjacent contacts and voltage measured between the other two. The Si substrate serves as a back gate. (b) Schematic cross-sectional view of H-terminated SOI(001) showing localized states, as we describe in the text.
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Figure 2
Sheet conductance as a function of back-gate voltage for H-terminated SOI(001). (a) Graph for a 120-nm-thick Si template layer. The data are plotted in linear and log (inset) scales. The flat-band voltage $V_{FB}$ and the threshold voltage $V_{T}$ are extracted from linear extrapolations of the curve at high negative and positive gate voltages, respectively. Surface- and interface-related electrical information is determined from the low-conductance region (white region between $V_{FB}$ and $V_{T}$ ). The insets show the band diagrams at the oxide-NM interface. Figure adapted from Ref. [23]. (b) Data (symbols) and simulation fits (lines) of conductance-voltage measurements of H-terminated SOI(001) for three different Si template thicknesses: 77, 120, and 220 nm. The curves are shifted along the voltage axis to have the sheet conductance minima appear at zero back-gate voltage. Uncertainties in the NM thickness and the electrical measurements are sufficiently small so that the resulting uncertainty in the sheet conductance does not exceed the size of the data points shown in (b). (c) Comparison between the naive calculated minimum conductance, as we describe in the text, of the NM bulk and experimental data (containing both bulk and surface effects) for $G_{\min}$ shown in (b) for 77-, 120-, and 220-nm-thick Si NMs.
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Figure 3
Diagrams for bands at three back-gate voltage conditions for a H-terminated Si(001) NM. (a) The sheet conductance–voltage curve for a 77-nm-thick Si NM. Unlike the curves presented in Fig. 2, the curve here is not shifted along the voltage axis. (b)–(d) are simulated diagrams of the positions of bands and the Fermi level across the Si NM at three different voltages: $V_{g} = - 250 V$ (accumulation), $V_{g} = - 96 V$ (at conductance minimum), and $V_{g} = 96 V$ (inversion). The values of $V_{g}$ , from $- 210$ to 120 V, are limited by the range of the voltage source. For simplicity, the only band bending shown in these diagrams is due to back-gate voltage. The value of $E_{F}$ at the surface is described as $E_{FS}$ in the text.
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Figure 4
Measured sheet conductance-voltage curves of a 77-nm-thick H-terminated Si NM before and after short-time low-temperature annealing at $270 ° C$ .
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