A logical qubit in a linear array of semiconductor quantum dots

We design and analyze a logical qubit composed of a linear array of electron spins in semiconductor quantum dots. To avoid the difficulty of fully controlling a two-dimensional array of dots, we adapt spin control and error correction to a one-dimensional line of silicon quantum dots. Control speed and efficiency are maintained via a scheme in which electron spin states are controlled globally using broadband microwave pulses for magnetic resonance while two-qubit gates are provided by local electrical control of the exchange interaction between neighboring dots. Error correction with two-, three-, and four-qubit codes is adapted to a linear chain of qubits with nearest-neighbor gates. We estimate an error correction threshold of 1e-4. Furthermore, we describe a sequence of experiments to validate the methods on near-term devices starting from four coupled dots.

Single electron spins in isotopically enriched silicon can have coherence times much greater than a millisecond [40,43,45,46], and electrically controlled exchange gates can be performed in tens of nanoseconds [27, 32- * ncodyjones@gmail.com 34,36,39,45,47]. Electron spins can also be controlled using microwave magnetic resonance, for which high-fidelity gates have been demonstrated [40,48,49]. Quantum dots have a promising path for extensibility since they are compatible with techniques for semiconductor fabrication and integration that were developed for classical computing, though the small feature sizes pose near-term challenges. A linear array of exchangecoupled dots is perhaps the most accessible design in which to demonstrate a logical qubit.
The proposed quantum-dot logical qubit is within reach of near-term experiments, but it also has the potential for extending to multiple logical qubits. The hardware platform is a linear array of silicon quantum dots where control operations are restricted to the electrically controlled exchange interaction between neighboring dots and global magnetic-resonance pulses that target all electron spins. The simplicity of the control scheme is favorable for producing multiple-dot devices, and we show how to adapt simple error correction such as repetition codes to this hardware. The components of the error correction scheme can be demonstrated in intermediate proof-of-concept experiments, as has been done in other qubit technologies [15,18,21,23,24,26,[28][29][30].
We assert that a logical qubit must have four characteristics to be extensible, in addition to the DiVincenzo criteria for a quantum computer [50]. These are: 1. Error threshold -The system must be able to run an error-detection procedure that itself introduces errors at some tolerably low probability to allow for a threshold error rate [51,52]. For stabilizer codes, this error detection is stabilizer measurement [53][54][55].
2. Fault tolerance -Any single fault is detectable, meaning that the logical qubit must be able to detect errors on its constituent physical qubits in all single-qubit Pauli bases [56]. 3. Parallel measurements -The logical qubit must have the ability to perform error-detection mea-surements at multiple locations simultaneously, where an extensible system has a number of measurement apparatuses proportional to the number of physical qubits [57]. Otherwise, error detection will not keep pace with error generation as the system extends. 4. Extensible encoding -The logical qubit must have an encoding strategy that is capable of extending to correct any number of errors [51,52,55,[57][58][59].
For stabilizer codes, this means code distance can increase without compromising any of the preceding criteria.
The logical qubit proposed here is designed to satisfy all of these criteria. Though the requirements might seem obvious, the sequence of experiments in Section IV is designed to specifically demonstrate each of these capabilities in silicon quantum dots. The scope of this paper is a proposal to design and test the simplest logical qubit in a linear array of silicon quantum dots. Based on recent results in SiMOS dots [27,40,60], we design spin-control protocols and error-correction instruction sequences. The hardware instructions and error correction are co-adapted to each other, as device fabrication favors simplicity while error correction favors more control of the qubits. Finding a viable experiment path to satisfy these competing design challenges is the central result of this paper. Our error correction schemes are simple two-, three-, and fourqubit quantum codes that have been mapped to the linear array of qubits [61][62][63], because alternatives like the surface code [8,[64][65][66] and Bacon-Shor code [67][68][69] are not effective in a linear geometry [70][71][72]. Our logical qubit is supported with simulations of error correction that can be compared with other proposals [13, 55, 62-64, 66, 68, 69, 73-80]. Finally, we are careful to note that a purely linear architecture is not extensible to an arbitrary number of qubits, for the simple reason that a single defective qubit anywhere results in two non-interacting arrays. Our present scope is limited to a logical qubit requiring at most 20 dots, so we do not examine this matter in detail. However, to establish viability of the proposal, we comment briefly in Section V on strategies for handling imperfect dot yield using results from faulty quantum-communication networks.
This paper is structured to show how the capabilities of the quantum-dot hardware and the instruction scheduling for error correction are closely integrated. The control operations in Section II are designed to be minimal, supporting extensibility, yet sufficient for the error correction in Section III. The proposed quantum-dot platform limits the set of control instructions to favor simplicity in the hardware, but the error correction must adapt to this restrictive control. The building blocks of error correction in Section III form a natural sequence of experiments, described in Section IV, for culminating in a logical qubit. The information gained from each experiment is directly related to the role of the QEC building blocks in the ultimate logical qubit. This experimental path provides milestones towards a logical qubit, and the measured performance of the building blocks can be used to predict performance of a logical qubit.

II. CONTROLLING SPINS IN A LINEAR ARRAY
This section describes the hardware platform for the proposed logical qubit, with an emphasis on reducing device complexity as much as possible while still supporting error correction. Figure 1 depicts a device architecture for a line of exchange-coupled quantum dots, similar to the devices demonstrated in Refs. 27 and 31 and employing a microwave ESR antenna as in Ref. 81. In this section, we first present the chosen methods for spin initialization, control, and measurement supported by this architecture. Second, we perform numerical simulations to estimate performance and identify areas of emphasis in characterizing and mitigating noise. Finally, we show how the sequencing of control operations, which we call "tick-tock control," implements an instruction set that is sufficient for quantum error correction. This transition to a logical-qubit encoding is specifically adapted to this SiMOS proposal to work around limitations in the available spin-control operations.

A. Fundamental Control Operations
The set of spin-control operations is designed to be as simple as possible to support a logical qubit. Furthermore, all control operations needed for the logical qubit have been demonstrated in silicon quantum dots. These include electron-spin resonance (ESR) [40,42,46,49], electrically controllable exchange interaction between spins in neighboring dots [27, 32-34, 39, 45], and electrically controllable preparation and measurement of two spins in the singlet/triplet basis using Pauli blockade [39,45,[85][86][87].
To favor extensibility, the logical qubit implements global ESR addressing of all spins (as in an ensemble experiment) [46,88,89], instead of selective ESR addressing of single spins [40,42,49]. Single-spin addressing is in principle possible with narrow-band microwave pulses, but this approach becomes increasingly difficult with many spins in the device, due to the increasing number of distinguishable frequencies which must be handled within a limited control bandwidth (a problem known as "frequency crowding" [28,90]). Addressing all spins simultaneously with broadband ESR avoids frequency crowding and the associated cross-talk errors, though this approach clearly limits what control is possible.
Global ESR is also beneficial for dynamical decoupling [91]. Dynamical decoupling is needed for two reasons in our proposal. First, the combination of an external applied magnetic field and an inevitable dis-   [82][83][84]. (c) Alternative top view where readout is implemented using single-electron transistors (SETs) located near the dots [27,40]. This example has 14 dots, which corresponds to a logicalqubit demonstration described in Section IV. tribution in electron g-factors leads to an inhomogeneous distribution of Zeeman energies. By applying echo pulses simultaneously to all spins, as practiced routinely in bulk magnetic resonance in inhomogeneous magnetic fields [46,92], one can coherently control many spins with broadband pulses without requiring a reference oscillator for each spin. (We note, however, that when the number of spins is low enough, the capability of selective ESR addressing of single spins is useful for testing and calibration.) A second reason for dynamical decoupling is to correct for dynamic phases that occur during two-qubit operations in our proposal, which employ electrically gated exchange interactions in the presence of large and controllable g-factor differences. As we discuss in the next section and has been demonstrated experimentally [27], these combined phenomena enable two-qubit controlledphase (CZ) or controlled-NOT (CNOT) gates. As elab-orated in Ref. 93 in the context of donors in silicons, these gates employ some robustness to high-frequency noise due to their use of adiabatic modulation of energy gaps, but they do incur dynamic phases during the adiabatic ramping. While such phases could be tracked in principle, they are also subject to low-frequency noise sources, and so it is preferred to refocus these phases entirely using dynamical decoupling.
The device schematic shown in Fig. 1 is configured with one gate electrode per quantum dot. The insulating oxide (such as AlO x ) between the metal gates produces a natural tunnel barrier between adjacent dots, as has been observed in experiments on SiMOS two-qubit devices [27]. The exchange coupling between adjacent qubits Q i and Q i+1 is achieved by applying a differential voltage between gates G i and G i+1 , to "detune" the electric potentials of the two dots. It is also possible to configure devices with an additional "exchange" gate between each pair of qubit control gates (labeled G i here), and such an approach has been used in Si/SiGe quantum dot devices [31,45,47,94]. If no exchange gate is used, then it will be necessary to adjust all gates simultaneously, via a self-consistent algorithm, to correct for the effect of cross-talk between gates when an exchange operation is applied between a specific pair of qubits, or pairs of qubits. Without electrical control of the tunnel coupling, the exchange energy J between each pair of spins is controlled by detuning their relative electrochemical potential; turning on J for one pair will require similarly shifting the electrochemical potentials of dots to the left and to the right to prevent unintended exchange with neighboring spins. A potential solution to applying exchange between any non-overlapping spin pairs simultaneously is to set the potential at each dot to one of two values, V (0) and V (1) . Starting from one end of the line of dots, assign potentials (0) or (1) such that neighboring dots have the same potential to turn off exchange and different potentials to "detune" and activate exchange. Since J is an exponential function of voltage, inhomogeneity in tunnel coupling can be handled by shifting voltages as needed only slightly from this simplistic model, so that small detunings will still have negligible exchange while large detunings will be designed to match the tunnel coupling of any dot pair and implement a uniform exchange operation in constant time for all dots.
In addition to global ESR for single-qubit control and dynamical decoupling, as well as the exchange interactions for two-qubit gates, our fundamental control operations include singlet preparation for ancilla qubits. A spin singlet |S = (|↑↓ − |↓↑ )/ √ 2 is simple to prepare in a small dot since it is the two-electron ground state. When a second-electron tunnels into a quantum dot from a thermal bath, a rapid equilibration generates the singlet ground state as long as the electron temperature and the electron Zeeman energy are substantially less than orbital or valley energies; temperatures around 100 mK and fields on the order of a tesla are easily sufficient for high-fidelity singlet preparation in SiMOS, where singlet-triplet splittings often exceed 1 meV [95]. This process may also be reversed for projective singlet-triplet measurement; if a double quantum dot is electrostatically biased into a regime where a two-electron state in a single dot is the ground state, the singlet will occupy this ground state while any symmetric spin-triplet will occupy an excited state due to Pauli blockade [96]. The distinguishable charge signature of the excited state enables distinguishing spin singlet from triplet via charge sensing. See Refs. 32, 39, 45, and 95 for more discussion. The next section examines the performance of these control operations, and Section II C describes how to implement all of the gates needed for error correction.

B. Experimental State of the Art and Simulated Performance in SiMOS Qubits
All of the spin-control techniques in preceding sections have been demonstrated experimentally in silicon quantum dots. To support a logical qubit, important measures of performance for each operation are speed and fidelity, in an extensible platform. Most of the control operations have been rigorously benchmarked, and here the results are already approaching the low error rates required for a logical qubit: high-fidelity singlet preparation, measurement in the singlet-triplet basis, ESR control of individual spins, and memory lifetimes exceeding a millisecond. An exchange-based CZ gate was recently demonstrated [27], and as we discuss below this gate could have a fidelity sufficient to support QEC for a reasonable level of charge noise. This section analyzes the recent experimental demonstrations and applies numerical simulations to predict the performance of control operations in a logical qubit.
The Hamiltonian describing qubit control in this section concerns the spins of two singly-occupied dots, a and b, with spin operators S j and total z-spin projection m = m a + m b . This Hamiltonian may be written is the average of and ∆g[V (t)] the difference of g-factors for the two dots; these are both functions of the time-dependent applied detuning voltage V (t). These g-factor differences cause differences in the Zeeman energy between dot pairs, which we notate is also a function of V (t). ESR-based spin manipulations are implemented via transverse microwave magnetic fields with modulated Rabi frequency Ω(t)/2. Note that external field B 0 points in theẑ direction and the oscillating field Ω(t) points in thex direction. Concerning non-coherent behavior, it has long been expected, as well as observed in ensemble studies, that electron spins in enriched silicon have long coherence times [2,46,[97][98][99][100]. Recent experimental demonstrations on single-spin qubits have validated this expectation. The relaxation time T 1 is greater than 1 second [101], so coherence time is limited by spin dephasing due to fluctuations in the magnetic environment. With a concentration of 800 ppm 29 Si, a dephasing time T * 2 as long as 120 µs has been demonstrated [40]. Recent investigations have examined the extent to which T * 2 is limited by low-frequency magnetic noise [43,48], which can be suppressed with dynamical decoupling schemes. The coherence time with decoupling has been extended to 1.2 ms with one pulse and 28 ms with multiple pulses [27,40]. A donor-bound spin in enriched silicon achieved an even longer coherence time [43], showing that there is further opportunity for improvement. Spin-control operations have been experimentally implemented in 1 µs or less [27,40], which is four orders of magnitude shorter than the decoupled coherence time. In the remainder of this section, we will not include these sources of dephasing, and rather focus on control errors, as these are likely to dominate performance in silicon logical qubits.
Preparation and readout in the singlet-triplet basis may utilize spin-to-charge conversion via Pauli blockade [5]. The method has recently been demonstrated in enriched Si/SiGe devices [45] with a readout visibility of 98%, where loss of visibility includes both preparation and measurement errors. This experiment was performed at magnetic fields near zero. At higher magnetic fields, two effects alter the use of Pauli blockade for initialization. First, at substantial magnetic fields, the g-factor variations lead to substantial differences in the Zeeman energy, ∆E Z , between a dot-pair. Considering Eq. (1), as one ramps from the spin-singlet ground state (|↑↓ − |↓↑ )/ √ 2 at high J to a lower value of J, eventually one reaches a regime where ∆E Z > J, at which point singlet and m = 0 triplet states begin to coherently mix. If intending a fully singlet initialization, one must either ramp quickly enough to avoid this mixing, refocus this mixing with a calibrated pulse sequence, or choose to instead prepare the |↑↓ state by adiabatic ramp down in J as in [32,39]. The latter choice is likely the most robust, and was recently considered for a larger-scale architecture in Ref. 102. An increased magnetic field may also reduce singlet (or |↑↓ ) fidelity when the energy splitting between the m = 0 states and the excited m = 1 state (i.e. |T − = |↓↓ ) decreases with B field. As outlined below, the operation of the SiMOS device at higher field strengths (up to 1.5T) is beneficial for faster CZ operation times. The large valley splitting in the SiMOS devices, measured to be 0.3-0.8 meV [101] and substantially larger than observed values in Si/SiGe devices [45], permits the use of higher fields before degradation of the Pauli blockade process. For example, with valley splittings this large, fields of order 1.5 T, and electron temperature around 100 mK, the probability of initializing into a thermal excited state is less than 10 −6 in principle. In practice, initialization and readout fidelity are limited by noise in control and readout electronics.
Controlled-phase entangling gates based on exchange have been analyzed and experimentally demonstrated extensively in the literature [27,103,104]. The example realized in SiMOS [27] is performed via an adiabatic pulse on the electrostatic detuning towards the (0,2) chargestate anticrossing. If J(V ) is the dominant term of this Hamiltonian, the exchange operation would implement swap rotations. However, the combination of a non-zero B field and a g-factor difference ∆g(V ) = g a (V ) − g b (V ) splits the energy levels of the spin states |↑ a ↓ b and |↓ a ↑ b , and the nonlinearity in the eigenvalue spectrum near the avoided crossing introduced by J(V ) allows a controllable phase shift which has produced controlled-Z and CNOT two-qubit gates between SiMOS quantum dots [27].
As the duration and fidelity of the CZ gate depends in part on g-factor differences between dots, it is important to characterize what values of ∆g are achievable. Disorder perturbations at the Si/SiO 2 interface lead to a stochastic and bias-dependent variation in gfactors. Figure 2 illustrates a randomly generated distribution of electron g factors for a linear chain of 20 qubits, as well as the g-factor tuning range, based on statistics from measurements on SiMOS devices [27]. In the event where two neighboring dots have small ∆g at zero electrostatic detuning, the difference can be increased with Stark shifting by choosing whether to detune the dots towards (2,0) or (0,2) charge configuration [27,40,101], noting that this would yield a favorable configuration for detuning potentials (0) and (1) along the chain as discussed in the previous section. In a recent experiment, the minimum energy splitting at B 0 = 1.4 T was ∆E Z = ∆gµ B B 0 = 20 MHz×h, with 10 MHz tuneability in each electron spin.
From preliminary estimates, simple square pulsing of the CZ operation with observed values of ∆E Z can achieve a two-qubit gate fidelity above 99%, but substantially higher fidelity is accessible through pulse shaping. In particular, adiabatic pulsing [93] has several advantages, principle among them being a resilience to some noise processes. In the adiabatic limit, pulsing into the avoided crossing and back realizes a combination of Zeeman phase shifts and a non-linear phase shift due to J(V ). The nonlinear phase shift is given entirely by the time integral of J(V ), which we here notate as ξ = J[V (t)]dt/ . The integral is over a sufficient time to fully capture a voltage pulse V (t) which brings J(V ) to and from a negligibly small value. The total adiabatic unitary evolution for the two spins is then given by where ω 0 (V ) =ḡµ B B z and In practice, the adiabatic limit is maintained by assuring that the frequency bandwidth of a J[V (t)] pulse lies well beneath the minimum value of ∆E Z [V (t)]/ . If the total nonlinear phase shift satisfies ξ = π, one achieves a maximally entangled CZ gate in addition to local singlespin phase shifts. These single-spin phase shifts are substantial, however, and subject to magnetic and charge noise, the latter due to the electric-field dependence of g j . Rather than attempting to compensate for these phases and accept errors due to low-frequency magnetic or charge noise, we instead employ an approach where we decouple these phases, as in Ref. 93 and illustrated in Fig. 3. Denote by X j a π pulse for spin j, and break our J(V ) pulse into two halves each satisfying ξ = π/2. Then under perfectly adiabatic conditions, where U CZ is a controlled-phase gate and S j = Z j is a single-qubit S-gate, which may be corrected via g-factor manipulation or by a frame update. No extraneous magnetic phases need be tracked in this decoupled CZ gate. Two sources of error are expected to limit the fidelity of this CZ gate, and these are considered in simulations indicated by Fig. 4. These simulations use a standard detuning model for J(V ) and a linear model for ∆g(V ), both informed by Ref. 27 and indicated in Fig. 4(a). In the J(V ) model, the tunnel coupling t c between dots is assumed to decrease for very small V , but saturates to a constant at large detuning V , where [39]. The chosen value and bias dependence of ∆g(V ) for this simulation are typical values from measurements of devices similar to the one in Ref. 27. Simulations use two Gaussian voltage pulses which satisfy ξ = π/2 interspersed with ideal single-spin π pulses as in Fig. 3. The simulation integrates the evolution due to these Gaussian pulses from −5σ t to 5σ t , where σ t is the root-mean-square temporal pulse width.
As indicated in Fig. 4(b), Gaussian pulses in V (t) lead to sharply peaked pulses in J[V (t)] for short σ t and to smoother, broader pulses for long σ t . These shapes are especially critical for the influence of charge noise, which is introduced as a randomly sampled noisy voltage δV (t). Ensembles of δV (t) functions are filtered from Gaussian white noise to produce the noise spectral density S V (f ) = A 2 /f , including a low-frequency cut-off corresponding to a 1-hour calibration timescale. This 1/f voltage noise mimics the expected influence of electric field noise from a variety of possible sources in a real device by modeling it as a single noisy voltage. A clear noise enhancement at the peak value of J[V (t)] is visible in Fig. 4(b), especially for the shorter pulse (lighter blue line); this is because the noise insensitivity I = J/|dJ/dV | rapidly decreases at high J for the detuning mode of operation [47]. The result of integrating the Schrödinger equation for these chosen pulse shapes is shown in Fig. 4(c), in which infidelity is given by the normalized trace-distance between the simulated, imperfect unitary and the ideal unitary of Eq. (4) under perfect adiabatic and noise-free conditions. Figure 4(c) uses the particular gate-referred charge noise amplitude A = 5 µV, a value comparable but somewhat improved relative to observed charge-noise either deduced from CZ oscillation decay in Ref. 27 or measured in similar MOS devices in Ref. 105.
The red curve of Fig. 4(c) shows the infidelity due to non-adiabatic behavior, which dominates at short pulse widths σ t but then falls rapidly with increasing σ t . The cyan curve indicates infidelity due to randomly sampled 1/f charge noise. This contribution to gate error may be decomposed into two sources. In the long-pulse limit, the limiting noise comes from charge-noise-induced fluctuations in g-factor, since this error increases with pulse length following a trend proportional to |∆g[V (t)]| 2 dt, as indicated by the green line in Fig. 4(c). At the min- for two different values of σt, including added voltage noise δV (t) with spectral noise density SV (t) = A 2 /f . These sample traces use a rather high value of A ∼ 30 µV to allow the noise to be visible on this scale. (c) Simulated infidelity of the adiabatic CZ gate. The red line results from simulating with no charge noise but examining infidelity due to non-adiabatic behavior. The cyan line considers strictly adiabatic evolution but adds charge noise by Monte-Carlo integration using sampled voltage noise as in (a), in this example with A = 5 µV. The charge-noise-induced infidelity (cyan line) decreases due to exchange noise, for which the primary trend indicated by the blue line follows 10(A/I peak ) 2 , where I peak = J/|dJ/dV | is the insensitivity [47] at peak J. For longer pulses the chargenoise-induced infidelity increases due to noise on the g-factor; the green trend plot is |∆g[V (t)]| 2 dt/(500 Grad/sec). The thick gray line is the total infidelity, estimated as the sum of the diabaticity (red) and charge-noise (cyan) contributions.
imum of infidelity relative to root-mean-square pulsewidth σ t the dominant noise source is an imperfect nonlinear phase from the integral over a noisy J[V (t)], which is dominated by charge noise at the peak of the exchange pulse. This noise source is therefore proportional to (A/I peak ) 2 , where I peak is the insensitivity at the peak of the exchange pulse. This contribution decreases for longer pulses which have a lower peak value of J, as indicated by the blue line. This error source could be reduced with symmetric exchange pulsing if an additional gate were available to modulate the tunnel barrier between dots [36,47]. There are important tradeoffs to consider between the additional electrostatic tunability offered by exchange gates and the increased device complexity from doubling the number of gates, but we defer the matter to other investigations in the literature [27,36,47]. The minimum total infidelity occurs around σ t ≈ 300 ns for these parameters, at which, over a broad range of A, the minimum infidelity scales as A 2 . The pulse width providing this minimum of course varies approximately linearly with the constant and voltage-dependent g-factor differences, which vary from dot pair to dot pair, but the dependence on these parameters of the minimum fidelity reached at the optimum pulse length is sublinear, allowing a substantial range of g-factor variation with infidelity comparable to the simulation shown in Fig. 4.
Our simulation of CZ infidelity has not included imperfections in single-qubit operations, such as the decoupling π-pulses. However, existing experimental implementations of cryogenic ESR give strong encouragement that these pulses can be achieved with high fidelity. Through the use of an on-chip transmission line [81], ESR control of single electron spins in SiMOS devices has been demonstrated with benchmarked control fidelity of as high as 99.6% [40,48]; another experiment with a micromagnet in Si/SiGe dots realized 99% fidelity [49]. However, as the number of electron spins in the device increases, frequency crowding becomes a notable issue, so the global ESR scheme introduced in the previous section would have all spins controlled by a common ESR transmission line. High-fidelity control of spin ensembles has been demonstrated in magnetic resonance [92], where composite pulse sequences like BB1 are used to correct for systematic over-rotation errors [106,107]. Global ESR on all spins in this proposal will require such broadband pulsing since the expected spread in values for electron g factor will lead to a spread in Zeeman energies of tens of MHz at B 0 = 1 T. The ability to electrically Stark shift the electron g-factor provides another resource for maintaining high-fidelity control using only global ESR pulses [27,101].
We finally note that several optimizations of the CZ gate discussed here are available and may be analyzed in future work. The Gaussian pulse shape for V (t) chosen in our analysis was not an optimized choice; shaped pulse sequences for exchange [108] and adiabatic CZ [109,110] gates have been employed in other contexts and allow for some optimization of fidelity. Further, the simple singlepulse dynamical decoupling routine we have employed could be extended to multipulse sequences to further suppress g-factor noise, which ultimately limits fidelity for very long pulses. Optimization of dynamical decoupling, especially in conjunction with the identification of bias regions of high insensitivity, can lead to drastic improvements in fidelity in the presence of charge noise [93].

C. Tick-Tock Protocol
All of the necessary gates for a logical qubit can be produced by deliberate sequencing of the following spincontrol operations: preparation of spin singlet, global ESR, and the exchange-driven CZ gate. We call our scheme for controlling quantum-dot spin qubits "ticktock" control, because control pulses are sequenced into two alternating time intervals, called simply tick and tock. The transitions between tick and tock are defined by applying global Hadamard gates using ESR [46,88,89]. Exchange-driven CZ gates are selectively implemented within tick or tock intervals [27]. Finally, twospin singlets are prepared, coupled to data by CZ gates, and measured in singlet-triplet basis, as explained below.
The tick-tock protocol can implement any CNOT between neighboring spins by appropriate timing of the exchange pulse. The Hadamard gates that transition between tick and tock intervals transform each CZ gate [27] into a CNOT gate, using the feature of the Hadamard gate that it interchanges X and Z operators [88]. Figure 5 shows a circuit diagram [59] that illustrates how any CNOT between neighboring qubits can be implemented by selectively performing a CZ gate in the appropriate tick or tock interval and merging with neighboring Hadamard gates. Unlike CZ, CNOT is not a symmetric gate, so the orientation depends on which qubits participate in the gate and whether it occurs in a tick or tock interval. The convention here is that the control qubit is odd-numbered in a tick interval and even-numbered in a tock interval. The unmatched Hadamard gates in Fig. 5b, which only occur at the beginning or end of the experiment, can be ignored since the single-spin data qubits are in an arbitrary state at the beginning and end of the computation. As explained below, the data spins are initialized using the aid of two-spin ancillas for measurement, after the tick-tock protocol has started.
There are two types of qubits in tick-tock control. Data qubits that hold logical information will be single spins, and measurement uses two-spin "ancilla" qubits which span either the singlet-triplet or "flip-flop" (|↑↓ / |↓↑ ) basis. Within tick-tock control, this ancilla has the additional feature that it can be used in a "measurement gadget" to projectively measure a data spin in either X or Z basis, determined by timing of exchange pulses. Throughout this section, we refer to the ancilla as being in the singlet-triplet basis, although as noted in the previous section, higher initialization fidelity may lead to preferring the "flip-flop" basis, |↑↓ / |↓↑ , which is initialized adiabatically. An adiabatic initialization procedure can be adapted to the tick-tock protocol by performing the traversal in a tick interval when the CZ coupling gates are to be performed in a tock interval, or vice versa. For either basis, when combined with the CNOTs from tick- tock control, we can use this ancilla to make all of the measurements required for error correction. The measurement gadget is a tool for measuring data spins in X or Z basis. In addition to measuring a single data spin, the gadget can be extended to projectively measure a multi-qubit X-or Z-basis operator, such as X ⊗ X or Z ⊗ Z. Herein, we only consider measuring operators that are purely X or Z type, as this is sufficient for an encoding family known as Calderbank-Shor-Steane (CSS) error correction [59,111,112]. The measurement gadget works by applying a CNOT to one of the ancilla spins (either works due to symmetry) and a data spin. To measure in the X basis, use timing in the tick-tock protocol to put the control qubit of the CNOT on the ancilla spin (Fig. 6a). Using subscript "d" for data and "a" for ancilla, the CNOT transformation is where 2 is one of the triplets (apply Pauli Z to either one of the spins in the singlet), and |+ and |− are the eigenstates of X. Likewise, to measure in the Z basis, put the target qubit on the ancilla spin (Fig. 6b). In this case, the CNOT transformation is where X |S = (|00 − |11 ) / √ 2 is another triplet (apply Pauli X to either one of the spins in the singlet). In words, the singlet is converted to triplet if the data spin is |1 , the −1 eigenstate of Z. For Equations (5) and (6), measuring the ancilla as singlet or triplet performs projective measurement in X or Z basis (respectively) on the data spin.
The gadget expands to projectively measuring any multi-qubit X or Z operators by applying a CNOT with orientation specified above between the ancilla and each data spin covered by the operator. For example, when measuring Z ⊗ Z on two data spins, the ancilla will flip between |S and X |S for each data spin in the |1 state, and likewise between |S and Z |S for Xbasis measurement. Measurement of a two-qubit operator X ⊗ X (Fig. 6c) or Z ⊗ Z (Fig. 6d) is the fundamental operation in "parity-measurement" experiments that have been demonstrated in other qubit technologies [15,18,21,23,24,26,[28][29][30]. Figure 7 shows how to implement the parity-measurement gadget in a device with four quantum dots. This parity-measurement gadget is the first demonstration in the experimental path described in Section IV. Moreover, all of the experiments use the parity measurement gadget as a subroutine in codes for a logical qubit, so they are extensions of the procedure depicted in Fig. 7.
In addition to measuring parity, the measurement gadget is also used to initialize data spins. The data spins are loaded into dots in an arbitrary mixed state. Then the tick-tock protocol of periodic Hadamard gates is initiated, and measurement gadgets are used to prepare each data spin in either X or Z basis as needed for the computation. An extensible logical qubit will require readout apparatuses that are regularly spaced in the array of dots, so this initialization procedure can be performed in constant time. An alternative initialization technique is to prepare two data spins as a singlet, which is a valid encoded state for some error-correcting codes. The final operation needed for universality is magic-state injection, which can be achieved by preparing a |+ state using the measurement gadget and then using a voltage pulse on that dot to Stark-shift the electron g factor, implementing a phase rotation. For example, a π/4 phase shift prepares the magic state for a T gate, which can be distilled with other available gates, as studied in the literature [64,113,114].

III. LOGICAL QUBIT IN ONE DIMENSION
Implementing a logical qubit requires detailed instruction sequences to perform encoding, decoding, and logical gates that incorporate error detection. The ticktock scheme in Section II places significant constraints on which gates are available, though it is still sufficient to implement error correction. In short, the main challenge for the proposed logical qubit is that any encoding scheme requires two-qubit gates between qubits that cannot all be local in a linear arrangement. The non-local interactions must be mediated by SWAP gates, and we discuss the significant prior work in this area below. This section describes the instruction sequences for two-and three-qubit repetition codes, as well as a four-qubit error detection code. By convention, the codes are identified by the number of data qubits, though ancillas for error detection are also required. These codes are all closely related to the error correction proposal by Shor [56], and they appear to be the simplest codes that can be implemented in a linear array. The codes also provide a sequence of experiments that demonstrate the essential features of a logical qubit, which are described in Section IV. We briefly describe the notation used in this section. The Pauli operators will be denoted as X or Z, and for multi-qubit operators the tensor product will be implicit such as XX. When needed, subscripts will index which qubit a Pauli operator acts on, and missing subscripts are implicitly the identity; for example, X 1 X 3 is a tensor product with identity operator on the second qubit and any others in the system. The +1 eigenstate of the X operator is denoted |+ = (|0 + |1 )/ √ 2. Encoded operators and states for a quantum code are denoted with a bar, such asX or |0 . Diagrams in this section use the quantum-circuit representation for its compactness, and these diagrams can be expanded to implement the ticktock protocol as shown previously in Fig. 7. The "weight" of a Pauli operator is the number of non-identity terms in its tensor-product expansion into single-qubit Pauli operators [59]; for example, weight(X 1 X 3 ) = 2.

A. Background on Error Correction in Constrained Geometries
For many qubit technologies, including quantum dots, long-range coupling is challenging. Several investigations into quantum error correction attempted to address this problem by studying codes that require only local interactions for qubits on a lattice in a finite number of dimensions. The toric code introduced by Kitaev [115] was specifically designed to have local stabilizer measurements in two dimensions (albeit the surface of a torus). The surface code and cluster-state computation emerged as variants of the toric code, preserving the important local-stabilizer feature while introducing boundaries for planar embedding or otherwise modifying the code to suit a particular architecture [8,64,65,76,114,116,117]. Another code family with similar properties are the color codes [80,[118][119][120][121][122][123][124][125], which also have local stabilizers. Surface and color codes are prominent examples of topological codes, which are codes that have local stabilizers and increase code distance by extending the size of the code [72]. A code with similar properties is the Bacon-Shor code [67,68], which is a subsystem code with local "gauge" operators in two dimensions. However, it is not topological because its stabilizers are not local.
Topological codes are not suitable for a linear nearestneighbor (LNN) architecture because they cannot have a threshold in one dimension [70][71][72]. Nevertheless, these codes provide instructive lessons. Many topological codes have good thresholds [64, 66, 76-78, 80, 126], and this seems to result from the local stabilizers [66,80]. Specifically, local stabilizers can be measured with short sequences of gates, limiting the potential for error propagation. Although the codes in this proposal are not topological, the stabilizer-measurement circuits are similarly compact; they use one-or two-qubit ancillas for low-weight measurements, as in surface codes [8,64,76,78,116,117,127] and Bacon-Shor codes [67][68][69].
As we stated in the Introduction, a logical qubit must have the ability to increase code distance. The main alternative to topological codes is code concatenation, where codes are nested inside of codes [59], which is the approach taken in this proposal. There have been encouraging results in thresholds with concatenation [6,52,69,128], as well as investigations into two-dimensional and LNN architectures [61-63, 68, 74, 75, 126, 129]. Knill demonstrated that small quantum codes (such as the four-qubit code studied here) can be effective when concatenated [6]. Although the thresholds calculated in that proposal are very high (3% or greater), the model for  SWAP is decomposed into three CNOTs, and the CNOT-followed-by-SWAP gate is two CNOTs, using a circuit identity [59]. qubits assumes arbitrary connectivity that cannot be realized with only nearest-neighbor interactions. Subsequently, Stephens and Evans developed an implementation of the subsystem four-qubit code in a LNN geometry [63]. Our four-qubit encoding adapts these methods to the operations that are available when using tick-tock control. We also apply the same SWAP patterns [61,63,74] and syndrome measurement to construct two-and three-qubit repetition codes as intermediate demonstrations towards a logical qubit.

B. Linear Nearest-Neighbor Error Correction: Instruction Set and Design Rules
Many quantum codes do not adapt well to a linear geometry; for example, topological codes cannot have a threshold in one dimension [70][71][72]. Fortunately, past work has established methods for error correction in a linear or bilinear array of qubits by concatenating small codes [61-63, 74, 130], and we apply these methods to our logical qubit proposal. Our adaptation makes some adjustments for the quantum-dot system we envision, and in the next section we introduce the tile formalism, which is a conceptual tool to aid the design and analysis of concatenated codes. The tile formalism is a strategy for building a logical qubit using nearest-neighbor gates in a linear array of qubits, and it is based on a set of design rules that prevent some of the pathological errors that can occur in LNN circuits.
We restrict the instructions used for error correction to a small set, which we call the standard set for an LNN architecture, or "standard-LNN," shown in Fig. 8. This set of instructions is closely related to CSS codes [111,112], as standard-LNN instructions are sufficient to encode, decode, and detect errors for any CSS code [59,69]. Moreover, any standard-LNN encoded gate can be constructed solely from standard-LNN instructions, making this set a natural choice when using code concatenation. The standard-LNN set consists of free, idle, preparation and measurement in both X and Z bases, all combinations of CNOT on two qubits (including SWAP and CNOT followed by SWAP), and magic state injection. The instruction "free" is used to designate a qubit that is unused in that instruction cycle; by construction, it always follows measurement. In contrast, idle applies to a qubit that has a defined state but is not changed in that instruction cycle. We include the magic-state injection instruction since it is needed for universality [6,113] [113]). The five two-qubit gates are all combinations of CNOT gates [59]. The instruction "free" differs from "idle" in that a free qubit (temporarily) has undefined state and carries no information, whereas an idle qubit does carry information. At the hardware level, the distinction may only be a labeling, but the instructions will have different encoded representations after code concatenation.
to be out of our scope. We note that magic-state protocols based on CSS codes can be implemented by the standard-LNN set [113,114]. Notably absent from this set are other Clifford gates, such as Hadamard and the S = √ Z phase gate. However, they are not transversal in all CSS codes, nor are they needed for our encoding schemes.
The Hadamard gate is frequently included in instruction sets, so we comment briefly on how an instruction set that lacks Hadamard can still effectively implement quantum logic. There are two common use cases for a Hadamard gate for which alternative constructions with the standard-LNN are equally efficient (or more so). The first is to interchange X and Z bases after preparation or before measurement, such as in syndrome measurement circuits [59]. Since preparation and measurement in both bases are in the standard-LNN set, this case is already handled. The second common application of Hadamard is in H/T sequences for approximating arbitrary single-qubit gates [131][132][133][134]. The Hadamard gates can be removed by merging two consecutive Hadamard gates and the intervening Z-axis rotation, and then replacing the composite gate sequence with an X-axis ro-tation: He −iθZ H = e −iθX . The X-axis rotation can be generated by a magic state having a distillation protocol that is complementary to that for the Z-rotation magic state by converting Z stabilizers to X and vice versa; this is equivalent to applying transversal Hadamard to the original code, which is another CSS code that can be implemented using standard-LNN instructions. A single remaining Hadamard gate at the beginning or end of the sequence can be implemented with magic states [64].
To make our analysis of error correction tractable, we adopt the following circuit design rules that will restrict the possible error events that can occur: 1. Use only standard-LNN instructions at level L − 1 to encode all standard-LNN instructions at level L, beginning with tick-tock control at level 0.
2. Never perform a two-qubit gate, including SWAP, between two data qubits in the same code block. Allowable pairs for two-qubit gates are data qubit and ancilla, two data qubits from different blocks, and in some cases two qubits in the process of encoding or decoding a block (examples discussed in next section).
3. For codes with weight-two stabilizers, use a single ancilla qubit to measure stabilizers, such that a single failure causes at most one data error.
We have already motivated the first rule by noting that the standard-LNN set is directly related to concatenation of CSS codes. The second rule prevents a single gate failure from introducing a weight-two error into a single code block. The final rule similarly ensures that a single failure in the syndrome extraction circuit will introduce at most one error into a data block. When a CSS stabilizer is measured with a single ancilla, a single failure can introduce at most a number of data errors that is half the weight of the stabilizer, rounded down [53]. In the next section, we will describe encoding circuits for small codes using these design rules, which will simplify analysis of error propagation.

C. Encoding Schemes
We consider three closely related encoding schemes for an LNN architecture, namely the two-and three-qubit repetition codes [56,59] and the four-qubit subsystem code [6,63,67]. These are small and simple codes that satisfy our design rules, but they can be concatenated to increase code distance. All three codes implement the standard-LNN instruction set, making them interchangeable layers in concatenation, and they provide intermediate experiments towards a logical qubit, as described in Section IV.
The encoded logic gates are grouped into blocks of instructions called "tiles," which provide a simple scheme for scheduling instructions to operate a logical qubit. We can view the instructions for an LNN architecture in a two-dimensional quantum circuit diagram where the vertical dimension spans qubits and the horizontal spans time flowing to the right [59]. An efficient implementation of instruction parallelism will densely fill this diagram, so we introduce interlocking tiles as a simple but effective conceptual tool for instruction scheduling. Each tile is a sub-circuit consisting of nearest-neighbor gates on a small set of adjacent data qubits and syndrome ancillas. We specify a tile to encode each standard-LNN instruction in each of the three codes considered here. Note that tiles manipulate encoded states, so they only align with other tiles from the same code.
The tile formalism ensures proper logical-qubit construction, as we now explain. The tiles naturally implement code concatenation by recursively building tiles at level L from tiles at level L − 1, where the hardware instructions are level 0. The tiles fit together perfectly in space and time, so they provide a simple method to efficiently construct concatenated LNN circuits. Each tile satisfies the LNN design rules, ensuring that circuits composed exclusively of tiles satisfy these constraints also. The tiles bring syndrome ancillas into contact with all data qubits for error detection. Finally, each tile moves the ancilla qubit(s) across a code block, leaving the other side open for an interleaved two-qubit gate (described below). Tiles provide all these features while also making instruction scheduling very simple. Each tile has a guarantee of logical correctness, which makes it easy to verify any circuit composed of tiles.
The most complex circuit for an encoded standard-LNN instruction is for a two-qubit gate, so this sets the tile size for a given code. The CNOT tile for the twoqubit, bit-flip code is shown in Fig. 9. The tiles for bitflip and phase-flip repetition codes are very similar, so we show one version of each tile and describe in words the small modification for its complement in the other code. The tile for a two-qubit gate consists of a "SWAP diamond" [63,74] followed by error detection. These are CSS codes, so encoded CNOT can be implemented transversally [59,111,112]. As shown in Fig. 9, data qubits from two code blocks are interleaved using SWAP gates, then a transversal CNOT is applied, then SWAP gates separate the data qubits back into their blocks. These three steps form a diamond-shaped circuit that gives all tiles their diamond shape. Note also that a nearly identical tile can implement any combination of encoded CNOT gates on the two code blocks (there are five such combinations), including SWAP and CNOT followed by SWAP, by modifying just the transversal operations in the middle of the SWAP diamond (shaded yellow).
Error detection is essential for a logical qubit and will be placed at the end (i.e. right side) of every tile. Error detection is mediated by ancillas for syndrome detection [53,55,59,135], but these operations can potentially interfere with transversal two-qubit gates, which require interleaved data qubits. The SWAP diamond primitive works best when the data blocks are adjacent,  9. Tile for encoded CNOT in the two-qubit bit-flip code. The CNOT symbol in upper left is a visual guide, and we will use "bit-flip" or "phase-flip" to clarify when necessary. Input and output lines are labeled for convenience. Two code blocks A and B have their data qubits labeled with numeric subcripts. A core "SWAP diamond" of interleave, transversal CNOT, and separate operations are shown with distinct colored backgrounds. Error detection using ancillas follows in a diagonal pass through the blocks. These ancillas begin and end on "free" lines that are not encoded at the lower layer, which are at different positions before and after the tile. and any interspersed syndrome ancillas must be skipped over [63,130], increasing the size of the tile. Instead, we have syndrome ancillas sweep through each data block in a diagonal, "staircase" circuit as in Fig. 9. This sweeping action shuffles the syndrome ancilla to the other side of the block, while the data qubits move outward from the two-qubit gate just implemented. This rearrangment is desirable because the blocks that just interacted are now positioned to interact with different neighboring blocks. The tile in Fig. 9 is compact, with no qubits being idle at any time. Note also that the error detection sub-circuit in Fig. 9 is for the bit-flip code. The tile for CNOT in the two-qubit phase-flip code has the same interleave, transversal CNOT, and separate, but the error detection sub-circuit is different and is shown in a subsequent diagram.
In the tile formalism, a qubit is measured and prepared in the the same time as allotted for a two-qubit gate. Since the measure-and-prepare joint instruction acts on one encoded block, it occupies a half-tile, as shown in Fig. 10 for the two-qubit bit-flip code. This design choice is entirely motivated by the use of code concatenation. Although preparation and measurement may take much longer to execute than a two-qubit gate at the hardware level, an encoded two-qubit gate will be the largest tile, as it is composed of preparation, measurement, and twoqubit gates at a lower level. After a measurement quarter tile, the constituent qubits are "free," meaning they contain no quantum data and their state is temporarily unimportant (and unencoded at all lower layers). Similarly, preparation begins with a free input line. This can be seen in the input and output interface of the CNOT tile (Fig. 9); every tile for the same code implements the same interface. In Fig. 10a, constituent qubits are free for some number of instruction cycles since we delay preparation until required, to minimize accumulation of error.
Each half-tile instruction must be matched with another half tile to form a complete diamond-shaped tile, which also determines if this mate is the code block above or below (or no block if at the edge of the linear array). Each half tile shown in Fig. 10 is the top of a diamond, and the corresponding bottom-half tile is the mirror image about a horizontal line (not shown). Enforcing diamond-shaped tiles enables simple scheduling without erroneous overlap of instructions. Recall that each twoqubit gate tile has a diamond shape ( Fig. 9; the other instruction tiles conform to this pattern. While Fig. 10 only shows measurement and preparation in the same basis, one could also measure in X basis and prepare in Z basis (or vice versa) by combining the appropriate operations. The other half tiles are state injection (Fig. 11) and idle (Fig. 12). Figure 12 also shows the error detection subcircuit for the phase-flip code, which can be substituted into Fig. 9 to get the CNOT tile in the phase-flip code. Using combinations described above, this provides all of The preceding measurement is shown to complete the half tile, and the basis could be changed following Figure 10. Importantly, this tile alone is not fault-tolerant, because the CNOT can emit an undetected weight-two error. This is acceptable because the injection tile is used for magic states that must be distilled.  To see the advantages of using tiles for scheduling instructions, consider the circuit in Fig. 13 for concatenating a phase-flip code on top of a bit-flip code. We start with a phase-flip encoded idle from Fig. 12, then replace each instruction with its appropriate tile in the bit-flip code, such as a variant of Fig. 9 for any two-qubit gate. In this example, we have visually separated the tiles for clarity, but they actually fit together perfectly.
Every complete tile has sufficient syndrome information to realize the full distance of the code. For the two-qubit repetition codes and the four-qubit subsystem code (described below), this means that any single error within the tile is detected. Correcting errors with these codes requires concatenation and syndrome processing using message passing [6,63,128,136,137]. Appendix A describes the syndrome processing that is used in Section III D to estimate the break-even performance of the two-qubit code.
The three-qubit repetition code is an extension of the two-qubit code, and it can detect either one Z error (bitflip encoding) or one X error (phase-flip encoding). Con- catenating a bit-flip code with a phase-flip code produces Shor's nine-qubit code [56,59], which can detect a single error of any type. To identify errors with enough confidence for error correction, additional syndrome measurements are required. This can be seen in the idle half tile in Fig. 14, where a total of four measurements are needed, two for each stabilizer generator of the code. The redundancy in error detection circuits is needed for a tile to reliably measure the error syndrome, avoiding a scenario where a single gate failure could cause a logical error by misreading the syndrome [53,55]. The width of the tile in time must match the CNOT tile described below, so there are several periods of just free or idle instructions on the left side of the idle tile. To save space in Fig. 14 and subsequent figures, this waiting time is represented by a white slash across the tile. The encoded two-qubit gate for the distance-three code, shown in Fig. 15, requires additional error detection. Some weight-two errors produced by a single faulty SWAP gate in the interleave stage can propagate through a transversal CNOT to a weight-three error event across both blocks, which would not be correctable unless it was detected earlier. An additional error-detection subcircuit is inserted after interleave and before separate (shown in colored regions as before) to catch this error, though doing so displaces other operations. This additional syndrome measurement is inserted into the block from which a logical error can propagate to the other block during the transversal operation; for the bitflip code (shown in Fig. 15) this is the control block of the encoded CNOT, whereas for the phase-flip code this block is the target. The remaining tiles for measurement, preparation, and injection are shown in Fig. 16. As with the two-qubit code, measurement and preparation can be arranged in any combination.
The four-qubit code that we consider is effectively the same as the smallest (i.e. distance-two) Bacon-Shor code [63,67,68], making it closely related to concatenated repetition codes. This code has weight-four stabilizers, so syndrome measurement requires special attention to avoid introducing undetectable errors. Before describing syndrome measurement, we will be specific about which four-qubit code we are using. It is a variant of the [ [4,2,2]] code studied by Knill [6], but only one of the logical qubits is used. The reason for this is that designing circuits for intra-block operations between the two logical qubits and handling correlated logical errors on them are challenging problems that we leave for future work. In keeping with the nomenclature for Bacon-Shor codes, we call the unused logical qubit a "gauge qubit" [67,68]. The logical qubit has encoded operators X L = X 1 X 2 andZ L = Z 1 Z 3 , and the gauge qubit has The four-qubit code has two stabilizers, X 1 X 2 X 3 X 4 and Z 1 Z 2 Z 3 Z 4 . Measuring a weight-four stabilizer has a potential problem where an error in the middle of the syndrome circuit could introduce a weight-two error that is logical and undetectable (X 3 X 4 =X L ). To solve this problem, we use a two-qubit ancilla |Φ + = (|00 + |11 ) / √ 2 to measure both stabilizers, as shown in the idle tile in Fig. 17. In addition to providing the value of both stabilizers in a Bell-state measurement, this circuit will also detect the introduction of anX L error from a fault in the syndrome circuit. Preparation and measurement in the Bell basis could be implemented using separate tiles for |+ and |0 preparation followed by CNOT, but a more efficient construction is shown in Fig. 18; at the physical layer, Bell preparation and measurement will need to be decomposed into available hardware instructions. The CNOT tile in Fig. 19 employs the same syndrome circuit in both blocks and the SWAP-diamond shape as in previous codes.
The half tiles in Fig. 20 are also designed to prevent an undetected logical error resulting from a single fault. The encoded measurements are transversal and automatically fault tolerant, so we focus on the preparation circuits. In particular, the circuits have the property that a single error from any CNOT will either be detectable or affect only the gauge qubit, just like the error-detection circuits of Figs. 17 and 19. Preparing |+ in Fig. 20a is simpler than preparing |0 in Fig. 20b, because the only weighttwo errors emitted by the CNOTs in panel (a) areX L andZ G , both of which act trivially on |+ . However, any LNN CNOT between data qubits can emit anX L or X GXL error, so preparing |0 requires the use of an ancilla. The circuit in Fig. 20b prepares |0 in a faulty   then measuresZ L with an ancilla to detect aX L error that could be generated by one of the CNOTs. Consider also the injection tile in Fig. 20c. The CNOTs here can emit logical errors, as described above, but this is acceptable since state injection is never fault tolerant and the magic state would need to be distilled anyway. Finally, the idle tile in Fig. 20d is just idle operations on the code block followed by syndrome measurement.
We have organized our encoded instructions into tiles, FIG. 17. Idle tile for four-qubit code. A Bell state Φ + = (|00 + |11 ) / √ 2 is used to measure the syndrome, because it can also detect weight-two errors introduced by the errordetection circuit. The two-qubit ancilla is measured in the Bell basis (lower-right, denoted "B") to detect X and Z errors simultaneously.
because each tile is self-contained for error correction. Each tile has sufficient syndrome information to process errors within the tile, up to the capabilities of that code. The details of processing the syndrome are analyzed in Appendix A, and the performance of the encoding schemes under standard error models is simulated in the next section.

D. Simulations of Logical Qubit Performance
The performance of a logical qubit depends on the likelihood of errors and how effectively they are corrected. In this section, we simulate some of the LNN encoding schemes of the previous section to provide performance targets for control operations. The simulations use a simplified error model consisting of independent Pauli errors applied after every operation (including idle), following a common convention in the literature [6,52,64,66,68,69,73,76,80]. When an error occurs in a two-qubit gate, the gate is followed by one of Error Detection   FIG. 19. CNOT tile for the four-qubit subsystem code. As with the other codes, any combination of encoded CNOTs between the two blocks can also be implemented by modifying the gate in the center of the SWAP diamond.
the 15 non-identity Pauli errors with equal probability. Although such a simplified error model cannot represent all quantum error processes, the simulations still provide guidance as to which spin-control operations require further improvement in fidelity. As has been observed in past work, the threshold for error correction requires simulating logical error rate for several different code distances [6,52,63,64,66,68,69,76,80,136,137]. More-  FIG. 20. Half tiles for measurement and preparation in the four-qubit code, in (a) X basis and (b) Z basis, as well as (c) state injection. As before, the measurement and preparation bases can be different by combining the appropriate sub-circuits. over, concatenation is necessary for distance-two codes like the two-qubit and four-qubit codes, as they can only detect errors in a single layer of encoding [6,136,137].
We simulate encoding a logical CNOT "extended rectangle" [73] for the two-qubit and four-qubit codes. The three-qubit code is not shown because the matter of handling inconsistent syndrome measurements complicates both syndrome processing and how one defines an extended rectangle; to keep our scope contained, we leave detailed analysis of this code to future work. Each simulation inserts randomly generated Pauli errors into the circuit for an encoded CNOT at one to four layers of concatenation (two-qubit code) and one to two layers (fourqubit code), which makes use of the Gottesman-Knill theorem [59] for efficiently simulating Clifford circuits. The error model is depolarizing noise following every gate (or randomly negating a measurement), similar to other works in the literature [6,52,64,66,68,69,73,76,80].
The results of Monte Carlo error simulations for the two-qubit code are shown in Fig. 21. In this simulation, a logical CNOT gate is encoded in one to four layers of concatenation that alternates between bit-flip and phase-flip encoding. Two methods of estimating logical failure rate are employed, Monte-Carlo sampling and malignant-set sampling [63,69]. In Monte-Carlo sampling, we generate errors independently for each gate according to a physical error parameter and count the number of logical failures. In malignant-set sampling, we create configurations of k errors and count the fraction of configurations that lead to logical failure. The logical failure rate is then given by Pr(fail|k errors)Pr(k errors), (7) where N is the number of gates. Since each gate has an error with the same probability p, the second term is simply the Bernoulli distribution, The first term on the RHS of Eqn. (7) is estimated by sampling from k-error events and determining the fraction that lead to failure, incorporating the appropriate weighting factors for the different error channels on oneand two-qubit gates, and preparation and measurement. We explicitly verify that no single error will lead to failure in the level-four concatenated two-qubit codes. We also truncate the sum when additional terms have no discernible affect on the plot in Fig. 21; for example, k max is 6 for level one and 25 for level four. These simulations suggest a threshold for the two-qubit code around 10 −4 . The crossing of the level-one and level-four logical error rates occurs at p = 9.5 × 10 −5 , while the crossing of level-two and level-four curves occurs at p = 3.1 × 10 −4 . Being more precise about the threshold would require computationally intensive simulations at higher levels of concatenation, but for now the 10 −4 estimate provides a useful reference point for an LNN architecture.
We also simulate the four-qubit code, as shown in Fig. 22. The crossing of the logical-error-rate curves for layers one and two of concatenation is sometimes referred to as a "pseudo-threshold", which here is 3.8 × 10 −4 . It has been observed before [63] that the threshold for further concatenation of the four-qubit code in a LNN array is slightly lower than this pseudo-threshold. Although we leave detailed threshold simulations to future work, the results are consistent with Fig. 21 in suggesting that a logical qubit in an LNN architecture would require error rates around 10 −4 .
We make a few comments on the resources for the encoded CNOT. Whereas the two-qubit code requires four layers of concatenation to correct a single fault, the threeand four-qubit codes only require two layers. Consider comparing the two-and three-qubit codes. The tiles of the three-qubit code are larger (such as Fig. 15), but fewer layers of concatenation means that a distance-three encoded CNOT has about 70% the gate count of the level-four CNOT for the two-qubit code. With fewer Error bars are 90% confidence intervals estimated from the data. The solid curves are produced by malignant-set counting or sampling, as described in the text; the logical error rate is given by Eqn. (7), after the coefficients are estimated. The correspondence between the two methods is a consistency check. We explicitly verify that the level-four encoding corrects any single fault.
error locations, we are optimistic that the three-qubitcode threshold would be similar to the two-qubit code, and perhaps the former is slightly higher. Similarly, the CNOT in the concatenated four-qubit code requires only 20% the number of gates as the comparable CNOT in the concatenated two-qubit code, while the pseudo-threshold in Fig. 22 is very similar to that of the two-qubit code. The experiments in Section IV make use of the twoqubit and four-qubit codes for intermediate demonstrations toward a logical qubit, and the simulations here provide control fidelity targets for experiments to demonstrate a "signature" of error correction, as explained in Section IV. This signature is the characteristic quadratic dependence of logical error rate on physical rate when any single error is correctable, so failure requires two independent error events. Figures 21 and 22 show that this signature can be seen even at error rates above threshold, up to 10 −3 or higher, which allows an experiment to demonstrate the functionality of error correction by synthetically inserting error, even if the physical error rate is above threshold [15,18,21,23,24,26,28].

IV. EXPERIMENTAL PATH TO A LOGICAL QUBIT IN QUANTUM DOTS
This section proposes a sequence of experiments for developing a logical qubit in quantum dots, summarized in Fig. 23. The experimental path demonstrates all of the requirements for an extensible logical qubit from the Introduction. We describe the complexity of the device needed for each experiment and how the results inform the next step towards a logical qubit. The incremental sequence of demonstrations provides numerous opportunities to improve the device design using feedback from meaningful experiments.

A. Parity Measurement and Signature of Error Correction
The parity experiment implements the two-qubit code where an ancilla detects either one bit-flip or one phaseflip error (depending on choice of encoding), such as the half tiles shown in Figs. 10 and 12. This important experiment demonstrates the first criterion for a logical qubit, as parity measurement with an ancilla is a component of fault-tolerant error correction [24-26, 29, 30]. There are two single-spin data qubits and one two-spin ancilla, requiring four dots in total. If ancilla measurement is only available in one location in the dot array, then the ancilla will have to be swapped back to that position.
Since this device is relatively simple, it could take advantage of additional spin-control techniques that may not be extensible, such as single-spin addressed ESR and single-spin initialization [40].
The parity-measurement experiment was depicted in Fig. 7, with a prospective device layout of four dots and a charge sensor for readout. To show that the paritymeasurement process is working, one can inject errors into the qubits, as has been done in trapped ions [15,23], photons [21], superconducting qubits [18,28], and diamond NV centers [24,26]. The first indication that parity measurement works correctly is that injected errors should predictably increase the frequency of parityvalue flips. Second, the results of measuring the individual data spins should be correlated with the parity measurements [30]. Finally, if the data spins are initialized as |00 (for bit-flip code), then the probability of observing |11 at the end of the experiment should be substantially suppressed when no parity flips are detected, as such an event would require two independent bit flips [15,18,24,26,28,30]. This signature of error correction by post-selecting on not observing a parity flip can be observed in experiments that cannot demonstrate a complete logical qubit, as discussed in Section III D. By initializing states that are sensitive to errors of one type (e.g. bit flip), the signature can be seen in small codes that only correct that type of error, as in several experiments below. Similar recent theoretical work has considered experiments to show error correction is working for small surface codes with error rates near or above threshold [138,139].

B. Correcting One Error Type
The parity experiment can be extended by one dot (now five dots in total) to implement the three-qubit repetition code, such as the instruction sequence in Fig. 14. This device can both detect and correct either one bitflip or one phase-flip error, because the two parity measurements for the three-qubit code can uniquely locate one such error. Several recent experiments have demonstrated this encoding (or an extension of it) with an ancilla in diamond NV centers [24,26] and superconducting qubits [28,30].
The three-qubit-code experiment increases complexity by incorporating the parity measurement as a subroutine; there are now two stabilizers to measure, and each stabilizer must be measured twice. The control sequence for the three-qubit repetition code is shown in Fig. 24. This encoding can demonstrate a logical qubit that suppresses one type of error below that of its physical qubits [30]. Furthermore, it is a precursor to the final logical-qubit experiment below, which concatenates the three-qubit bit-flip and phase-flip repetition codes.

C. Detecting Any Single-Qubit Error
The smallest demonstration of detecting any singlequbit data error is the four-qubit code with just one ancilla (note that the construction in Section III uses two ancillas). This implementation requires six dots, but the resulting tiles are larger to reuse the single ancilla to measure two stabilizer generators. The new capability demonstrated by this experiment is detecting a single error of any type. Similar recent demonstrations include stabilizing a Bell state with ancillas [29] and the detection of errors in an encoded state (without ancillas, however) [16,23].
The next improvement to the four-qubit code is to have two measurement ancillas. This requires eight dots, and it demonstrates both measurement parallelism and the detection of any single-qubit error. This realizes the fourqubit code as presented in Section III, such as the tiles in Fig. 17.
Using 12 dots, one can concatenate the distance-two bit-flip and phase-flip codes, as shown in Fig. 13. The control sequence for the concatenated error detection is shown in Fig. 25. Using concatenation, this experiment is essentially three copies of the parity-experiment (Fig. 7) setup integrated together. The 12-dot experiment demonstrates two criteria for extensibility: concatenation and measurement parallelism. The code can detect at least one error of any type, which could realize error correction if the code were concatenated again to distance four, though this experiment is outside of our scope.
These intermediate experiments on the the path to a logical qubit demonstrate several of the extensibility criteria listed in the Introduction, in increasing levels of device complexity. The smallest four-qubit code shows the ability to detect both bit and phase errors, as well as the signature of error correction from before. Moving to two measurement ancillas enables detection of both error types in parallel. Finally, the concatenated twoqubit code demonstrates an extensible encoding procedure, such as encoded gates and measurements (see the tiles in Fig. 13). Collectively, the experiments to this point demonstrate all of the essential features for a logical qubit.

D. Logical Qubit Demonstrations
The logical qubit demonstrations are based on the nine-qubit code introduced by Shor [56,59], which is the concatenation of the three-qubit bit-flip and phaseflip codes. The first implementation is a minimal design that is compressed into 14 dots, comprised of nine data spins, three auxiliary data spins for an encoded block to measure the second-level syndrome, and one two-spin ancilla to measure the first-level syndrome in all four blocks. The number of physical qubits (13) is the same as the smallest surface code [65,127,138]. The additional idle time and SWAP operations to move this single ancilla around will penalize code performance, but the signature of error detection can be seen in the syndrome measurements even above the error-correction threshold [15,18,23,24,26,28]. This demonstrates many features of a logical qubit: syndrome measurement with an ancilla, code concatenation, and the ability to detect one error of any type.
The final experiment incorporates measurement parallelism, demonstrating all criteria for an extensible logical qubit. It is another implementation of the nine-qubit Shor code using 20 dots. Whereas the minimal logical  24, 26, 28, and 30. qubit in the previous section had a single measurement ancilla shared among all data qubits in four blocks, this design is the standard implementation of code concatenation where each block has a measurement ancilla, exactly as described in the encoding tiles of Figs. 14-16. This is four copies of the 5-dot experiment (detecting one error type) integrated together. The distinguishing features of this experiment compared to the 14-dot implementation are that it implements the tile formalism without modification and that measurement parallelism is employed, which is crucial for extensible error correction.

V. DISCUSSION
We have presented a proposal that addresses all of the essential requirements for a logical qubit in silicon quantum dots. To keep our scope contained, there are of course technology considerations that we have not analyzed in detail, which we will discuss briefly here to acknowledge their importance. We believe that current quantum-dot technology is ready to begin developing a single logical qubit and that further improvements in materials and fabrication, such as the work cited below, will occur alongside the experimental demonstrations of Section IV.
The tick-tock protocol implements ESR control addressing all spins simultaneously. The microwave power necessary to perform the global ESR control with high fidelity is dictated chiefly by the necessity to address spins which need to have different g-factors in order to perform fast CZ operations. This requires the ESR pulses to be "non-selective" despite the significant spread in resonance frequency of the individual qubits. However, once the g-factor spread has been characterized and, if needed, tuned, adding more spins does not require additional power. Heating due to ESR pulses can be mitigated by using cavities to confine the microwave modes [92,140,141], but this presents other challenges for bringing metal electrodes to the dots. Ongoing work in superconducting qubits for combining complex electromagnetic environments with sub-Kelvin temperatures makes us optimistic that engineering solutions are possible here as well [12,81,142,143].
The possibility of defective quantum dots is an important consideration for extensibility, so we make a few comments on this topic. As we noted before, a single defective dot can disable a logical qubit when using LNN error correction. For the purposes of this proposal, we believe that current technology has sufficient yield (probability of successful dot fabrication) to reach 20 coupled dots in the near term. Schemes to handle imperfect qubit yield or qubit loss have been studied in errorcorrecting codes [144,145], qubit device designs [146][147][148][149][150][151], and quantum networks [152][153][154]. Similarly, iontrap proposals have studied how to effectively combine linear trapping regions with junctions to overcome the limitations of a strictly linear trap [4,9,[155][156][157][158]. In light of these methods, we expect that it is possible to arrange short linear segments of dots that meet in three-or four-way junctions, such as in Ref. 159, enabling enough connectivity to route information around defective dots and tolerate imperfect yield. However, developing such a scheme is outside our present scope.
We have focused our proposal on the SiMOS system, but it may certainly be adapted to other semiconductor quantum dot systems. Confining the quantum dots in a Si/SiGe heterostructure rather than against a Si/SiO 2 interface may reduce the effects of disorder and charge noise, at the expense of introducing smaller valley splittings which may impair singlet initialization and measurement [42,45,49,160]. The controllable g-factor shifts in SiGe might be substantially smaller than what is observed in SiMOS dots, so the proposal might require the introduction of induced magnetic field gradients [42,49,161,162]. Our scheme may also be feasible using a heterostructure based on III-V semiconductors, which have no valley degeneracy and may be engineered For generality, the tiles in Section III represent measurable qubits with just one line, but in tick-tock control the ancillas for measurement require spin pairs. These spin pairs begin as (Q3,Q4), (Q7,Q8), and (Q11,Q12), and they move during the experiment following this diagram. The spins could be initialized using techniques in Section II C to test error detection, and the experiment can be extended to more rounds by adding more tiles.
to have high Stark-tunable g-factor shifts [163]. There are inevitably large numbers of nuclear spins in III-V systems, requiring more reliance on dynamical decoupling. Encouragingly, dynamically decoupled coherence times approaching milliseconds appear to be feasible [37], although a fully hyperfine-compensating modification to our control scheme would require additional design in this case. Finally, our scheme could be adapted to the problem of substitutional donors coupled to SiMOS-like dots or spin-shuttling channels, in which case its implementation would resemble the schemes indicated in Refs. 93 and 164.

VI. CONCLUSIONS
We have presented a comprehensive proposal to develop a logical qubit in silicon quantum dots. The ticktock scheme in Section II C is an extensible way to control electron spins in quantum dots, and all of the constituent operations have recently been demonstrated with fidelity approaching the requirements of a logical qubit. Recognizing that a linear array of exchanged-coupled dots is the most realizable device design in the near term, we have adapted simple error-correcting codes to a linear, nearest-neighbor system. Using Monte Carlo simulations, we have estimated an error threshold of 2 × 10 −4 . Finally, we have described a sequence of experiments to demonstrate components of error correction and integrate those components into a complete logical qubit. The final logical-qubit demonstration is a linear encoding of Shor's original quantum code, and a successful demonstration here would be a compelling argument for viability of quantum-dot logical qubits. This appendix describes the syndrome-processing algorithm used in the simulations of Section III D, where information from syndrome measurements is used to estimate the most likely configuration of errors. The error model is a stochastic distribution of Pauli errors inserted after every control operation, idle period, preparation, and measurement [6,52]. Syndrome processing attempts to locate and correct errors by making the most probable assignment of error conditioned on knowing the syndrome measurements. The encoding tiles are self-contained for syndrome processing, meaning they do not share syndrome information or store it for later use. Instead, they calculate maximum-likelihood error by searching over all error events and selecting the one with maximum probability.
Tiles are self-contained -To implement error correction, we first ensure that every tile can effectively detect errors up to the distance of the code [58,59]. We say that such tiles are self-contained since they do not require syndrome information from any preceding tiles. The two-qubit and four-qubit codes are distance-two error detecting codes, so it is only necessary that any single error is detected by the next syndrome measurement on the block. We now list the cases to consider. The tiles in Figs. 9 and 12 are able to detect a single bit-flip or phase-flip error event, depending on choice of encoding. In the case of the two-qubit tile, the two blocks jointly detect errors in SWAP gates that propagate to both. The tiles in Figs. 10 and 11 have measurements that detect a single bit-flip or phase-flip error. The circuits in Fig. 10 for preparation of |0 and |+ have the property that any single error is detectable by the next tile. The state injection in Fig. 11 is not fault tolerant, which is allowable since it is used to inject magic states. The tiles in Figs. 19 and 20 have all of the same properties, with the ability to detect any single error event.
The distance-three repetition code has two additional matters to consider. First, each stabilizer generator is measured twice, and a measurement error could cause these results to disagree. When the stabilizer measurements are inconsistent, error correction is deferred until the next round and no corrective action is taken in that tile. If there is an error in the data qubits, it will propagate to the next tile on that block. Every tile can handle one incoming error on each block, so it would be the responsibility of the next tile to correct any error left uncorrected due to an ambiguous syndrome. Second, the possibility of two errors emitted by a SWAP gate is the reason for one additional syndrome measurement before the transversal CNOT in Fig. 15. If the syndrome is consistent for both blocks and the control block for bit-flip encoding detects error (target block for phase-flip code), then there is the possibility of an undetected error in the other block. This can occur when a SWAP gate emits two errors, one of which propagates through a transversal CNOT. The additional syndrome measurement is needed to catch this event.
Pauli channels and message passing -The error model where Pauli errors occur stochastically is known as a Pauli channel [6]. In this model, a random Pauli error can follow every standard-LNN instruction; additionally, each measurement has a probability of reporting an incorrect result. Pauli channels are convenient because they combine to other Pauli channels, they propagate through Clifford circuits to other Pauli channels, and the conditional error channel for a stabilizer code given syndrome information is also a Pauli channel. After correcting the syndrome, there is also a Pauli channel for the logical subspace, so there is a logical Pauli channel for every encoded standard-LNN instruction. Hence, just as we use standard-LNN instructions to encode that same instruction set at a higher level, there is also a Pauli channel associated with that encoded instruction. The parameters of this encoded Pauli channel are a function of the error channels for the constituent gates and the syndrome measurement outcomes. As a result, every standard-LNN instruction has an associated Pauli channel at all levels of encoding, which is an implementation of message passing [128].
Message passing (MP) is a natural extension of syndrome processing in concatenated codes. Note that in some contexts MP is known as belief propagation [128,165,166], and it is a standard tool for decoding some families of classical codes [167]. In the original formulations of code concatenation [55,59], each layer of encoding would perform maximum-likelihood correction of errors based on syndrome measurements. For the encoded operation, there is (at least implicitly) an error model that an encoded error occurred. Without MP, each layer commits to a correction, which has an implicit failure probability. With MP, each layer will still perform an assignment of error, but it also passes upwards to the next layer a measure of confidence (the message) that it made the right assignment. This confidence measure, which could be flags for weights of errors [6,63,136,137,168,169] or a Pauli channel [128], is based on the observed syndrome and messages from lower layers. Consequently, the next layer above is better informed by having the message and can make a better assignment of error. Reference 168 discusses how this procedure realizes the full distance of a concatenated code. Some form of MP is necessary for distance-two codes because they cannot assign errors in a single encoding layer [6], and Refs. [128,168] show that MP improves the performance of distance-three codes. For these reasons, we employ MP in our syndrome decoding.
Updating error likelihood using the syndrome -The gates within a syndrome-measurement circuit generate errors, and it is necessary to distinguish errors that propagate to measurement from those that do not. By exploiting the stabilizer structure of the codes studied here, any two-qubit Pauli channel following a CNOT gate can be approximated by single-qubit Pauli channels before  [6,128], where layer L is phase-flip encoded and layer L + 1 is bit-flip encoded. After each tile in layer L processes its syndrome, it passes a message containing information on logical errors to layer L + 1. In this example, the first five tiles in layer L have completed execution and syndrome processing; the extracted logical error channels are passed to layer L + 1, denoted as ε1 to ε5. The remaining instructions from layer L + 1 have not executed, so the corresponding error channels are shown in grey with dashed borders. When all 12 error channels are available, the tile at layer L + 1 will process its syndrome and pass an error message to the next layer above. and after the gate, as shown in Fig. 27a.
To calculate error likelihood, all instructions in an encoding tile are associated with a Pauli channel. At level 1, each Pauli channel is the assumed error model in the hardware for that instruction [6]. At higher levels of concatenation, each Pauli channel comes as a message from syndrome processing of the tile in a lower layer. Within a tile, syndrome processing is accomplished by searching all error events and re-weighting their probability according the observed syndrome, as follows. Every measurement has a probability of being faulty, which is also given by the hardware error model at level 1 or a message at higher levels. For each error event in the search, there is an anticipated syndrome result. Depending on the observed syndrome, the probability of this error having happened is re-weighted by Bayes' theorem from elementary probability. This probability-update procedure can be seen as a variant of the Viterbi algorithm [170].
After re-weighting all error events, the maximumlikelihood event is selected to update the Pauli frame [6, Residual errors from previous tile

Residual errors from previous tile
Residual errors sent to next tile Residual errors sent to next tile ε 9 ''' ε 9 ' ε 9 '' ε 9 Error information used for syndrome processing in a tile. (a) Substitution to convert two-qubit error channel to single-qubit channels, separating errors that are detected by the syndrome from undetected errors. (b) Location of error channels after substitution in a tile that is ready for syndrome processing. At the end (i.e. right side) of the tile, a few errors occur after syndrome processing and are not detected. These are passed as "residual" errors to the next tile, just as residual errors are passed into this tile from the left. 114]. The probabilities of other error events that would cause logical errors are combined into a logical Pauli channel that is passed as a message to the next level of encoding [6,63,128,136,137,168,169], as depicted in Fig. 26. Searching over all error events is computationally intensive in the general case, but it is tractable for these small tiles with a finite number of error locations. A few errors are not detectable in this tile. As shown in Fig. 27b, these are passed as "residual" error channels to the next tile on the same block for processing. Finally, after processing a two-qubit-instruction tile, the residual error channels for top and bottom blocks are correlated, and tracking such correlations would lead to an exponentially growing runaway in simulation memory; to prevent this, the distributions are "split" by calculating marginal distributions for the separate blocks and using this as an approximation for the closest uncorrelated joint-block distribution.
Bell-basis measurement and preparation in four-qubit code -The Bell-basis measurement/preparation tile in Fig. 18 requires some special processing of measurements. First, note that the "transversal" measurement/preparation operations do not follow the familiar pattern from CNOT tiles, but rather there is a mirroring in data qubits: (A 4 ,B 1 ), (A 3 ,B 2 ), etc. This exploits a mirror symmetry in the code where X L = X 1 X 2 = X 3 X 4 and so forth. The reason for this change is that it prevents correlated SWAP errors from introducing a logical measurement error. If one were to follow the typical interleave-transveral-separate pattern and replace the CNOTs in Fig. 19 with Bell-state measurement/preparation instructions, the tile would be logically correct but not fault tolerant since a single SWAP failure could corrupt the encoded measurement. The tile in Fig. 18 is transversal in a sense, and one can construct the logical operators X A L X B L and Z A L Z B L from combinations of the Bell-basis measurement on data qubits (note that superscripts "A" and "B" denote blocks). The joint-block stabilizers are also available for error detection.
The preparation circuit also merits some explanation. The mirrored transversal preparation of |Φ + in the data qubits creates a state that is close to the desired Φ + . It is a stabilizer state with the following stabilizer generators: The missing generators for Φ + are S A X and S A Z individually, which would also imply S B X and S B Z through com-bination with the existing joint-block stabilizers. The syndrome-measurement circuits in Fig. 18 will project into a state with the same set of stabilizer operators as Φ + , but possibly different parity values. The correction procedure is simple: if a stabilizer for a block is flipped, apply a corrective operation to a single data qubit, which will just be qubit 1 without loss of generality. For example, if the measured syndrome shows , then we apply a corrective Z A 1 (in the Pauli frame [6,114]). Since the syndrome measurements commute with the operators in Eqn. (A1), these operators are preserved. In particular, the joint-block stabilizers provide error detection, so we expect S A X and S B X to have even parity, likewise for Z stabilizers. If odd parity is observed, then a fault in the preparation circuit has occurred, but it is detected. Any single fault can be detected in this way, except for "residual errors" from the syndrome circuits, as in Fig. 27. These events can generate at most one undetected data error per block, which can be detected by the subsequent tile.