Simulation of memristive synapses and neuromorphic computing on a quantum computer

One of the major approaches to neuromorphic computing is using memristors as analogue synapses. We propose unitary quantum gates that exhibit memristive behaviours, including Ohm's law, pinched hysteresis loop and synaptic plasticity. Hysteresis depending on the quantum phase and long-term plasticity that encodes the quantum state are observed. We also propose a three-layer neural network with the capability of universal quantum computing. Quantum state classification on the memristive neural network is demonstrated. Our results pave the way towards brain-inspired quantum computing. We obtain these results in numerical simulations and experiments on the superconducting quantum computer ibmq_vigo.


I. INTRODUCTION
Neuromorphic computing is a brain-inspired computer paradigm in contrast with the von Neumann architecture [1,2]. According to the biological model of the brain, the information is stored and processed by a highly connected network formed of neurons, which provides the ability of learning, parallel and low energy cost computing, etc. Since the 1940s, it has been realised that how neurons wire up is essential [3]. Besides neuroscience, this observation also motives the development of computer programming, such as the neural network algorithms vastly used in today's machine learning technologies [4,5]. In term of the learning rule of neurons, spike-timing-dependent plasticity (STDP) is a biologically plausible model that has gained great attention in recent years [6][7][8]. In STDP, the synapse is strengthened or weakened depending on the temporal order between spikes of pre-and post-synaptic neurons [see Fig. 1(a)]. In this way, the brain can establish causal relationships between events.
Quantum computing uses quantum phenomena and is superior to classical computing in solving certain problems [9]. For example, to solve the integer factorisation problem, Shor's quantum algorithm takes polynomial time with respect to the integer size, which is exponentially faster than the most efficient known classical algorithm [10]. In the circuit-based universal quantum computer, information is encoded in qubits and processed with unitary gates [11]. This kind of quantum machines is still under development but already demonstrates the power of surpassing classical computers [12,13]. Because the quantum computer for large-scale computing is not available yet, variational quantum algorithms are proposed for the near-future applications [14][15][16]. Quantum neural networks are generalisations of classical artificial neural networks, in which unitary gates in the quantum circuit are taken as variables [17][18][19][20][21][22][23][24][25][26].
The memristor is a resistor with memory and one of the fundamental two-terminal circuit elements [see Fig. 1(b)] [27,28]. Its resistance decreases or increases depending on the input signal, i.e. the voltage or current. Memristance can explain STDP in biological synapses [29]. Since the first memristive device was found in 2008 [30], the application as hardware analogue of synapse in neuromorphic computing has been extensively investigated [2], mainly because memristive devices demonstrate behaviours similar to STDP [31,32].
In this paper, we propose memristor-like unitary quantum gates. These gates have the characteristic memristive property, i.e. hysteretic resistance state [28,30]. Given an oscillatory input state, the output-input observables display a pinched hysteresis loop. We find that the loop depends on not only the classical distribution but also the phase of the input quantum state, which reflects the quantum nature of memristive gates. Using these gates to mimic synapses, we observe the long-term potentiation (LTP) and long-term depression (LTD), which are crucial for learning and memory in the neural network [6,8]. We show that quantum information can also be encoded in a manner similar to the long-term plasticity. Therefore, a neuromorphic computer based on the memristive gates can process quantum information.
An artificial neural network with three layers is proposed as an example of the neuromorphic system based on memristive quantum gates, as shown in Fig. 1(d).
Numerical result: Experimental result: FIG. 2. Hysteresis loops of memristive gates. Here Z C in and Z C out represent the voltage and current, respectively. Details are in Appendix C.
Neurons in the input and hidden layers are qubits, and neurons in the output layer are classical bits. Two quantum layers are wired up by memristive gates, and output bits are measurement outcomes of hidden-layer qubits. Compared with the general quantum neural network [17], the number of variational parameters is significantly reduced with respect to the number of neurons and synapses. Each connection between an input neuron and a hidden-layer neuron is characterised by two variational parameters (i.e. weights), and each connection to an output neuron is characterised by only one parameter. We prove that such a three-layer memristive neural network is as powerful as a universal quantum computer [11] up to a polynomial overhead. The application of the neural network is demonstrate in quantum state classification tasks [22][23][24]34]. All the results are demonstrated with numerical simulations using QuESTlink [33] and experiments on the quantum computer ibmq vigo. An example circuit realisation of memristive quantum gates is given in Fig. 1(c). Alternative circuits are used in experiments for minimising the impact of errors. Details of numerical simulations and experiments are in Appendix.

II. MEMRISTIVE QUANTUM GATES
To find quantum gates with the memristive properties, we introduce a simplified picture of the memristor, which is different from actual memristive devices [30]. When we send the input current to the memristor, the current is transmitted or reflected depending on the state of memristor, and the state of memristor evolves depending on the input current. If the input current is from A to B [see Fig. 1(b)], the resistance of the memristor decreases. If the input current is from B to A, the resistance increases. We use one qubit to represent the current state: |0 C and |1 C denote currents from A to B and from B to A, respec-tively. We use another qubit to represent the resistance state: |0 R and |1 R denote transmission and reflection, respectively. In the extreme case, the resistance state can be completely flipped in one shot, then the memristor is the transformation The key point is that input states and output states of this transformation are both orthogonal. Therefore, it can be a unitary transformation, i.e. a quantum gate. Now, we consider the general case that the resistance state is rotated by a finite angle of π − 2θ when it is not saturated. The corresponding unitary transformation reads where basis vectors are sorted as |0 C ⊗ |0 R , |0 C ⊗ |1 R , |1 C ⊗ |0 R and |1 C ⊗ |1 R . When θ = 0, M θ can flip the resistance state in one shot as in the extreme case. When θ is finite, the gate transforms the input state |0 C ⊗ |1 R into |1 C ⊗ (cos θ|0 R + ie −iθ sin θ|1 R ), i.e. the current is reflected, and the resistance state is rotated by a finite angle. It is similar for the input state |1 C ⊗ |0 R . We can find that the influence of the input current on the resistance state is minimised at θ = π 2 . Many similar memristive gates can be constructed. For example, we can change the phases e iθ and e −iθ , and the gate is still memristor-like. We choose the phases such that the gate M θ can be used for encoding a quantum state and implementing universal quantum computing on the neural network, as we will show later.
In some scenarios, we want to use different qubits to represent the states of two terminals A and B. For example, we use two qubits A and B to represent the voltages of two terminals. We can modify the memristive gate by taking |0 C = |1 A ⊗ |0 B and |1 C = |0 A ⊗ |1 B . Then, a three-qubit memristive gate is M θ = M θ ⊕ 1 1 4 , where 1 1 4 is the four-dimensional identity matrix acting on the subspace of |0 A ⊗ |0 B ⊗ |µ R and |1 A ⊗ |1 B ⊗ |µ R , i.e. the state of memristor does not change when two terminals have the same voltage. Qubits A and B can also be used to represent the spike timings of two neurons when the resistance qubit mimics the synapse. Memristive quantum gates for multi-state current and resistance can be constructed in a similar way. In this paper, we focus on the two-qubit gate for simplicity.

III. MEMRISTIVE BEHAVIOUR
Let ρ C and ρ R be input states of the current qubit and resistance qubit, respectively. Then the output state after the memristive gate is ρ out = M θ ρ C ⊗ ρ R M † θ . If we consider mean values of the Pauli operator Z, we can find Ohm's law of the memristive gate, i.e. Z C out = Z R in Z C in , where Z C in = Tr(Zρ C ), Z R in = Tr(Zρ R ) and Z C out = Tr(Z ⊗ Iρ out ) play the roles of voltage, conductance and current, respectively. See Appendix B. Here, I, X, Y and Z are Pauli operators.
To demonstrate the hysteretic behaviour, we let the resistance qubit interact with a sequence of current qubits in the input states ρ . . one by one through memristive gates. These states have an oscillatory observable Z C in (t), and t is the label of the time. Driven by current qubits, the resistance state (i.e. the conductance) evolves with t, which results in the hysteretic behaviour. The Z C out -versus-Z C in (i.e. current-versus-voltage) hysteresis loops are shown in Fig. 2. We take ρ , and η = 1, i in (a) and (b), respectively. In both cases, Z C in (t) = cos(δφt). However, the phases of quantum states are different. As a result, hysteresis loops have different shapes.

IV. LONG-TERM PLASTICITY
In STDP, causal events increase the strength of a synapse, and acausal events decrease the strength, which are called LTP and LTD, respectively. LTP and LTD can be mimicked using the memristor [32]. In the memristive gate, the resistance state evolves driven by the current qubit. The output state of the resistance qubit is M θ,ρ C (ρ R ) = Tr C (ρ out ), where Tr C denotes the partial trace on the current qubit, and M θ,ρ C is a completely positive map depending on θ and the input state ρ C of the current qubit. The steady state of the map is ρ s = 1 2 (I + Z C in Z) (see Appendix D). Therefore, after the interaction with a sequence of current qubits in the same input state, the conductance of memristor converges to Z R s = Z C in , i.e. the classical information of the current qubit is encoded into the resistance qubit.
To demonstrate LTP and LTD phenomena mimicked using memristive gates, we take ρ C = |0 0| and ρ C = |1 1| to represent causal events in LTP and acausal events in LTD, respectively. We also take ρ C = |+ +| to represent stochastic events (SE) without a definite casual order, where |± = 1 √ 2 (|0 ± |1 ). The results of numerical simulation and experiments are shown in Fig. 3(a). In three-qubit memristive gates, we can use qubits A and B to represent spike timings of two neurons, which will lead to similar results.

V. ENCODING QUANTUM STATES
Memristive gates can also encode quantum information into the resistance qubit. In LTP and LTD pro- cesses, only the classical information is encoded because the phase information is not preserved. The current qubit is flipped or not flipped depending on the resistance state. Therefore two qubits are correlated in the Z direction in the output state, which damages the phase information. To restore the phase, we can measure the output current qubit in the X basis and adjust the phase of the resistance qubit: the identity gate I or phase gate Z on the resistance qubit is performed if the measurement outcome is |+ or |− , respectively. Accordingly, the map on the resistance qubit . Therefore, after the interaction with a sequence of current qubits in the same input state, the resistance state converges to ρ C , i.e. the quantum information is encoded.
The quantum state encoding is demonstrated in In the two experiments, the encoding fidelity reaches 97.672% and 97.638% after three memristive gates in (b) and (c), respectively.

VI. ARTIFICIAL NEURAL NETWORK
The neural network in Fig. 1(d) has three layers. The input layer and hidden layer are formed by M current qubits and N resistance qubits, respectively. Each connection between the two quantum layers has three labels (i, a, b) and two parameters (φ i , θ i ): The i-th connection is a composite gate M θi e −i φ i 2 Y ⊗ I on the a-th current qubit and b-th resistance qubit. Here, the Y -axis rotation is on the current qubit. We remark that these connections are time-ordered according to i because quantum gates are non-commutative. The output layer is formed by N classical bits. Each resistance qubit and the corresponding classical bit has a connection with only one parameter φ j : After a Y -axis rotation e −i φ j 2 Y , the resistance qubit is measured in the Z basis, and the outcome is the classical bit.

VII. UNIVERSAL QUANTUM COMPUTING
To implement the universal quantum computing on the memristive artificial neural network, we initialise input (current) and hidden-layer (resistance) qubits in states |0 and |+ , respectively. We can think of that resistance qubits form the register of quantum data, and current qubits conduct the computing. (i) A current qubit can write/read the quantum state of a resistance qubit by taking φ = θ = 0, as shown in Fig. 4(a), corresponding to transformations M 0 |ψ ⊗ |+ = |+ ⊗ |ψ and M 0 |0 ⊗ |ψ = |ψ ⊗ |0 , respectively. (ii) To perform a single-qubit gate, we let a current qubit carry the qubit state |ψ and prepare a resistance qubit in the state |0 by using write/read operations. Then, by visiting the resistance qubit twice with parameters shown in Fig. 4 which is a universal singlequbit gate. (iii) To perform a two-qubit gate on two resistance qubits, we use a current qubit to read the state of the first qubit ψ and let it interact with the second qubit ϕ [see Fig. 4(c)]. The output current state is written into the third resistance qubit. In this way, a controlled-NOT gate Λ X is performed. The corresponding transformation on three resistance qubits is |Ψ 1,2 ⊗ |+ 3 → |0 1 ⊗ Λ X |Ψ 2,3 , where |Ψ is the input two-qubit state, and the second qubit is the control qubit in Λ X . The universal single-qubit gate and controlled-NOT gate form a universal gate set [9].
Each controlled-NOT gate consumes one current qubit and one resistance qubit. The single-qubit gate can be implemented under the restriction that each current qubit can only visit a resistance qubit at most once. See Appendix F for details. Under this restriction, each single-qubit gate consumes three current qubits and two resistance qubits. Therefore, the overhead cost is polynomial.

VIII. QUANTUM STATE CLASSIFICATION
Now, we use the memristive neural network for the quantum state classification [22][23][24]34]. Input qubits are prepared in one of quantum states to be classi-fied |Φ k . Hidden-layer qubits are initialised in the state |+ . The probability distribution of output classical bits µ is p φ,θ (µ|Φ k ) given the input state |Φ k , where φ and θ are parameters of the neural network. We find the optimal parameters by maximising D = k =k D(p φ,θ (•|Φ k ), p φ,θ (•|Φ k )). Here, D is the trace distance between two distributions [9], which characterises how well two states can be distinguished according to the output µ.
Two examples are implemented. First, we use a network with two neurons in each layer, i.e. M = N = 2 to classify four Bell states. Because Bell states are orthogonal, they are completely distinguishable, which can be achieved by the neural network. Second, we use a network with M = N = 5 to classify two five-qubit ground states of the quantum Ising model in ferromagnetic and paramagnetic phases [35], i.e. the Greenberger-Horne-Zeilinger state |Φ ghz = 1 √ 2 (|0 ⊗M +|1 ⊗M ) and the product state |Φ + = |+ ⊗M . These two states are not orthogonal. We find that the maximum distance given by the neural network can reach the quantum upper bound, i.e. the trace distance between two quantum states [9]. If we turn off parameters φ by setting all φ to zero, only memristive gates are used in the classification. In this case, the distance can reach 0.94792, which is lower than the upper bound 0.96824 but is still above the classical value 0.9375, i.e. the distance given by a direct measurement in the Z basis on each qubit. Numerical data of the optimisation computing are in Appendix G. For the experimental implementation, we use the network shown in Fig. 5(a) to classify two-qubit ground states. In the numerical simulation, the distance can reach the theoretical upper bound 0.70711, which is reduced to 0.65673 (but still higher than the classical value 0.5) in the experiment using optimal parameters. The corresponding distributions are shown in Fig. 5(b).

IX. DISCUSSION
We have demonstrated that memristive quantum gates can mimic memristors and synapses, which are essential building blocks of neuromorphic computing. These gates are unitary transformations that are feasible in many physical systems [9]. Memristive gates are fully quantum compared with the memristance involving the weak measurement and dissipation in quantum systems [36][37][38][39][40][41]. The experiments are implemented using universal gates on a circuit-based quantum computer ibmq vigo. By engineering the interaction between qubits, it is also possible to realise a memristive gate directly in the time evolution. Synapses based on memristive gates can encode the quantum state in a way similar to the longterm plasticity, therefore, are capable of processing quantum information. We have demonstrated the supervised quantum state classification on the memristive neural network, which can also be used for the unsupervised learning [32]. These results pave the way towards the neuromorphic system in the quantum regime, i.e. a braininspired quantum computer.

ACKNOWLEDGMENTS
This work is supported by National Natural Science Foundation of China (Grant No. 11875050) and NSAF (Grant No. U1930403). YL thanks Tyson Jones for help on using QuESTlink.

Appendix A: Numerical simulation and experiment
We implement numerical simulations using QuESTlink, which is a library based on the framework of Quantum Exact Simulation Toolkit (QuEST). We perform experiments on ibmq vigo via IBM Quantum Experience.
In all the experiments, circuits are altered from Fig. 1(c) and optimised for minimising the impact of errors on ibmq vigo. In the hysteresis, LTP, LTD and quantum state encoding experiments, the qubit 1 is the resistance qubit, and qubits 0,2,3 are current qubits. In quantum state encoding experiments, we replace the measurement and feedback phase gate with a controlled-NOT gate, and they result in the same effect on the resistance qubit when gates are perfect. In the quantum state classification experiment, qubits 0,1,2 are used, and the roles (resistance or current) of qubits change in the circuit for minimising the number of two-qubit gates. More details will be given in the following sections.

Appendix B: Ohm's law
Consider the transformation of the operator Z ⊗ I, we have Therefore,

Appendix C: Hysteresis loops
In the numerical simulations, the resistance qubit is initialised in the state ρ (2) R = Tr C (ρ (1) out ); and so on. In this way, we can obtain output states of each gate. Then, at the time t, the voltage is Z C in (t) = Tr(Zρ out ), and the output conductance is Z R out (t) = Tr(I ⊗ Zρ (t) out ). In Fig. 2, small gray circles represent the numerical data of ( Z C in (t), Z C out (t)) with θ = 7π 16  On ibmq vigo, a qubit has direct gate coupling with at most three other qubits. Therefore, we implement the memristive gates between the resistance qubit and at most three current qubits. To demonstrate a full cycle of each hysteresis loop, we divide the cycle into four segments, i.e. four experiments, according to the four segments of the dashed lines. In the experiments, we take θ = 3π 8 and δφ = π 4 as the same as in numerical simulations of the dashed lines. For the segment started at t = s, we prepare the resistance qubit in the numericallycomputed output state ρ (s) R , and then we let the resistance qubit interact with three current qubits prepared in states ρ In the experiments, we decompose the memristive gate into elementary gates as shown in Fig. S1(c). Data of ( Z C in (t), Z R out (t)) are shown in Fig. S2. . Hysteresis loops of ( Z C in(t), Z R out(t)). Here Z C in and Z R out represent the voltage and conductance, respectively.

Appendix D: Steady states of maps
We use the Pauli transfer matrix representation. The input state of the current qubit is , and the input state of the resistance qubit is where I, X, Y and Z are Pauli operators. The Pauli transfer matrix of the memristive-gate maps M θ,ρ C and M θ,ρ C are We express the output state of the resistance qubit in the form ρ R,out = 1 The steady state of the map M θ,ρ C is the solution of the equation ρ s = M θ,ρ C (ρ s ). Express the steady state in the form ρ s = 1 We remark that ρ Z C = Tr(Zρ C ) = Z C in . Similarly, the steady state of the map M θ,ρ C is the solution of the equation ρ s = M θ,ρ C (ρ s ). Express the steady state in the form ρ s = 1 2 (I +ρ X s X +ρ Y s Y +ρ Z s Z), the solution is  Therefore, ρ s = ρ C .

Appendix E: LTP, LTD and quantum-state encoding
In the LTP and LTD numerical simulations, we let the resistance qubit interact with a sequence of current qubits in the input states ρ  Fig. 3(a).
Four LTP and LTD experiments are implemented on ibmq vigo, corresponding to four thick curves (with circles) in Fig. 3(a), respectively. From left to right, in the first experiment, the resistance qubit is initialised in the state |+ , and three current qubits are initialised in the state |1 ; in the second experiment, the resistance qubit is initialised in the state |1 , and three current qubits are initialised in the state |0 ; in the third experiment, the resistance qubit is initialised in the state |0 , and three current qubits are initialised in the state |1 again; and in the forth experiment, the resistance qubit is initialised in the state |1 , and three current qubits are initialised in the state |+ . We let the resistance qubit interact with three current qubits one by one through the memristive gate. The memristive gate is decomposed into elementary gates as shown in Fig. S1(c). We take θ = π 4 . After each memristive gate, Z R out is measured.
In the quantum-state encoding numerical simulations, we let the resistance qubit interact with a sequence of current qubits in the input states ρ (0) C , ρ (1) C , . . . , ρ (t) C , . . . one by one through modified memristive gates. The circuit of the modified memristive gate (encoding gate) is shown in Fig. S1(d). Because we are only interested in the state of the resistance qubit, the modified memristive gate can also be realised using the circuit shown in Fig. S1(e). The additional controlled-NOT gate is equivalent to a phase gate on the resistance qubit depending on the phase state of the current qubit. We take ρ 22 Z e −i 3π 10 X |0 and |ψ = e −i π 16 Z e −i 3π 32 X |0 in the two simulations. The resistance qubit is initialised in the state ρ (0) R = |+ +|. With this initial state, we compute the output state of the resistance qubit at each time t, i.e. ρ 16 . Then, the mean values of three Pauli operators P R out (t) = Tr(P ρ Two quantum-state encoding experiments are implemented on ibmq vigo, corresponding to two input states |ψ = e −i 7π 22 Z e −i 3π 10 X |0 and |ψ = e −i π 16 Z e −i 3π 32 X |0 of current qubits. In each experiment, the resistance qubit is initialised in the state |+ , and three current qubits are initialised in the state |ψ . We let the resistance qubit interact with three current qubits one by one through modified memristive gates. The gate is realised using the circuit in Fig. S1(e), in which the memristive gate is decomposed into elementary gates as shown in Fig. S1(c). We take θ = π 8 . After each memristive gate, P R out are measured, where P = X, Y, Z. The data are plotted as thick curves (with circles) in Figs. 3(b) and (c).
We can express states of the current qubit and resistance qubit as ρ (t) , respectively. Here, ρ P C = Tr(P ρ

Appendix F: Universal gates
Under the restriction that each current qubit can only visit a resistance qubit once if they are connected, the single-qubit gate can be realised as shown in Fig. S3. The connection-1 prepares the second resistance qubit (from left to right) in the state |0 . The connection-2 reads the state of the first resistance qubit |ψ into the second current qubit. The connection-3 corresponds to the first visit in Fig. 4(c). Then, the connection-4 writes the output state of second current qubit into the third resistance qubit. The connection-5 reads the state of the third resistance qubit into the third current qubit. The connection-6 corresponds to the second visit in Fig. 4(c). To understand the controlled-NOT gate, we only need to note that the memristive gate with θ = 0, i.e. M 0 , is equivalent to a controlled-NOT gate followed by a swap gate, as shown in Fig. S1(b).
To distinguish four Bell states we take M = N = 2, i.e. each layer has two qubits or classical bits. We find optimal parameters φ and θ by maximising the distance function The value of the average distance D/6 is plotted in Fig. S4(a), which reaches one at the end of the optimisation. The distance D is never larger than 1, and D = 1 means that two states are fully distinguishable with the successful probability one. The optimal parameters are φ = (0, −0.31973, 0, 0, −1.5708, 0) and θ = (0, −1.3065, 0, 0). We note that π 2 1.5708, and we can find that the distance is one for any values of φ 2 and θ 2 .
In the experiment of three-qubit neural network implemented on ibmq vigo, we optimise the implementation, i.e. minimise the number of two-qubit gates, as follows. We can find that only memristive gates M θ with θ = 0 are used according to optimal parameters. Each gate M 0 can be realised using two controlled-NOT gates, as shown in Fig. S1(b), which is equivalent to a controlled-NOT gate followed by a SWAP gate. Therefore, we can implement the neural network with optimal parameters as shown in Fig. S1(f): At the beginning, qubit-0 represents the resistance qubit (i.e. hidden-layer qubit), qubit-1 and qubit-2 represent current qubits (i.e. input qubits); To perform the first memristive gate, instead of physically performing the SWAP gate, the roles of qubit-0 and qubit-1 are exchanged after the first controlled-NOT gate, i.e. now qubit-1 represents the resistance qubit, and qubit-0 represents a current qubit; It is similar for the second memristive gate. The distributions of measurement outcomes obtained in the experiment are shown in Fig. 5(b). The distance between distributions of two ground states is 0.65673, which is lower than the theoretical value D(|Φ ghz , |Φ + ) 0.70711 but above D(q(•|Φ ghz ), q(•|Φ + )) = 0.5.