Enhanced connectivity of quantum hardware with digital-analog control

Quantum computers based on superconducting circuits are experiencing a rapid development, aiming at outperforming classical computers in certain useful tasks in the near future. However, the currently available chip fabrication technologies limit the capability of gathering a large number of high-quality qubits in a single superconducting chip, a requirement for implementing quantum error correction. Furthermore, achieving high connectivity in a chip poses a formidable technological challenge. Here, we propose a hybrid digital-analog quantum algorithm that enhances the physical connectivity among qubits coupled by an arbitrary inhomogeneous nearest-neighbour Ising Hamiltonian and generates an arbitrary all-to-all Ising Hamiltonian only by employing single-qubit rotations. Additionally, we optimize the proposed algorithm in the number of analog blocks and in the time required for the simulation. These results take advantage of the natural evolution of the system by combining the flexibility of digital steps with the robustness of analog quantum computing, allowing us to improve the connectivity of the hardware and the efficiency of quantum algorithms.


I. INTRODUCTION
Quantum computation has emerged in recent years as a promising technology which aims at solving problems such as the factorization of a composite number [1], studying quantum field theories [2,3], simulating quantum chemistry [4,5], fluid dynamics [6], or the simulation of complex systems [7][8][9][10] more efficiently than classical computation.Another reason for the increasing interest on the field of quantum computation is due to Grover's algorithm [11], which shows quadratic speedups when compared against classical search algorithms.This technology can be implemented in different quantum platforms, such us trapped ions, photonics, or superconducting qubits, among others.In this last platform, strong efforts have been performed to show an example in which a quantum processor outperforms any classical computer, milestone recently achieved by Google [12].This flourishing technology still presents a considerable number of challenges to be solved, such as increasing the number of high-quality qubits in a single quantum processor or achieving interactions among all qubits.These problems characterize the so-called Noise Intermediate-Scale Quantum (NISQ) devices [13], quantum chips comprising 50-100 qubits, which are still affected by significant noise.
With the objective of optimizing the currently available resources for quantum computation and, ultimately, implementing a useful quantum computer in the NISQ era, an alternative paradigm of quantum computing called digital-analog quantum computation (DAQC) [14,15] has recently been proposed.This approach aims at improving the performance of digital quantum computers by taking advantage of the robustness of the natural dynamics of the chip, instead of turning off the internal interactions [16].This approach has been proved theoretically viable when an all-to-all (ATA) Ising Hamiltonian describes the natural dynamics of the quantum processor, * mikel.sanz@ehu.esmeaning that DAQC achieves universal computation using ATA analog blocks along with single qubit rotations (SQR).It has also been given a decomposition of the quantum Fourier transform (QFT) using the DAQC paradigm [17].Furthermore, simulations show an improvement in the QFT implementation when reasonable assumptions regarding noise are made.At this point, it is remarkable the banged DAQC approach, in which the Hamiltonian is always on and the SQR are performed on top of the analog dynamics.It seems to pose advantages in the fidelity of the unitary matrices simulated when compared to the stepwise approach.However, the intrinsic interactions among the different qubits in a chip are not necessarily well described by an ATA homogeneous Hamiltonian.In fact, a physical quantum chip is expected to present only nearest-neighbour (NN) interactions, since ATA connections require a prohibitively increasing amount of wiring among the qubits.
In this Article, we design an algorithm that optimally simulates an arbitrary ATA Ising Hamiltonian employing as a resource a given inhomogeneous NN Ising model and SQR.This is achieved employing O(3L 2 ) analog blocks, i.e.NN evolutions, with L the number of qubits of the chip.Even though the particular dynamics considered as a resource is the ZZ Ising Hamiltonian, the proposed algorithm could be extended to other dynamics, such as the XX+YY Ising Hamiltonian.The simulation of the Hamiltonian is optimal in the number of blocks and the simulation time required.

II. GRAPH REPRESENTATION OF AN ISING HAMILTONIAN
The Ising Hamiltonian for L qubits can be interpreted as a weighted graph of L vertices, where the weight of the edge connecting the vertex i to the vertex j is g ij .If two vertices i and j are not connected, g ij = 0.
In this representation, an ATA Ising Hamiltonian of L qubits becomes a complete graph K L , i.e. a graph with edges among every possible vertex without repetition.On the other  hand, the NN Ising Hamiltonian is represented as a Hamiltonian path, that is, a path visiting all the possible vertices only once.
It is noteworthy to mention that an arbitrary Hamiltonian path is represented by a permutation of all the vertices in the graph.To recover a Hamiltonian path from a given vertex permutation, it suffices to connect with an edge the vertices that are adjacent in the permutation.An example of a complete graph, together with two Hamiltonian paths, are represented in Fig. 1, where we also show the vertex permutation of the Hamiltonian paths.
Notice that we are currently dealing with ZZ interactions and thus, different Hamiltonian path evolutions commute.This means that the final evolution will be the sum of all the Hamiltonian paths weighted by their respective evolution time.This last statement is summarized in the equation i e itiHPi(gj ) = e i i tiHPi(gj ) , where HP i (g j ) is a Hamiltonian that describes a ZZ interaction which has a graph representation of a Hamiltonian path with wights g j .This is understood in the graph representation as having as final graph the sum of all the weighted Hamiltonian paths.Our first task is then to split the complete graph, which represents the ATA Hamiltonian, into a set of Hamiltonian paths that will be later simulated using our resource (the NN Hamiltonian).This will allow us to efficiently decompose the ATA evolution in terms of Hamiltonian paths.
Partitioning a complete graph into a set of Hamiltonian paths resembles the Hamiltonian decomposition problem, which is about partitioning a complete graph into a set of Hamiltonian cycles.This last problem was solved by Walecki [18,19] in 1890, who used a construction in which one Hamiltonian cycle is rotated to get all the cycles that composes the complete graph.Using a similar decomposition schematized for 6 qubits in Fig. 2, we can decompose the complete graph into a set of disjoint Hamiltonian paths.These Hamiltonian paths are characterized by the vertex permutation where P k L ∈ S L , being S L the symmetric group for L elements, L the number of qubits and k ∈ Z such that 1 ≤ k ≤ L/2.j represents the j-th position of the vertex permutation.Note that k is just a label for the Hamiltonian path.
It is also noteworthy to mention that this partition is only valid for an even number of qubits.When dealing with an odd number of qubits, and hence, and odd number of vertex in the graph representation, we use the notion of single perfect matching.This involves using the same Hamiltonian path construction of Eq. 2, but allowing one Hamiltonian path to overlap with the rest.This will pose no problem in our later construction, since we will be able to selectively turn off the desired interactions.
In Fig. 2, we show an example for 6 qubits where we also depicted the corresponding Hamiltonian paths.Hence, the problem know consists on efficiently simulating these Hamiltonian paths to obtain the ATA evolution.

III. SWAPPING GATES
The next step is to obtain each of the Hamiltonian path connections using a NN Hamiltonian as a resource.For that, we will change the connections using a SWAP-like gate U that performs the operations The gate that changes the action of an arbitrary operator in a qubit to another qubit is the SWAP gate, defined as where the superindices 1 and 2 refer to the qubit on which the gate acts.However, as we only need to change Z gates, we have some degrees of freedom available.More precisely, the most general unitary gate that fulfils Eq. 3 is where 2 and α, β, γ ∈ R. Since we will later build this gate using inhomogeneous Ising Hamiltonians from the DAQC perspective, we will set α = γ = 0 and β = − 1 2 , obtaining the so-called iSWAP gate.The choice of parameters will minimize the amount of single qubit gates and analog blocks required, since We will focus now on obtaining a sequence of iSWAP gates acting on adjacent qubits that efficiently transforms a system with NN connections into a system with the desired Hamiltonian path connections.The reason to restrict ourselves to adjacent iSWAP gates is that we want to decompose them using NN Ising Hamiltonians as a resource.
For the sake of clarity, we will use U ij to represent the iSWAP gate between qubits i and j.We will first show how this operation transforms a system with NN couplings.The result will be a system represented by a Hamiltonian path in its graph representation.
If we sandwich σ k z σ l z , a gate that applies the Z gate to the qubits k and l, with the gate U ij , we obtain where we have defined the function τ ij as a permutation of the indices i and j, that is, a transposition.More precisely, if Basically, the U ij gate changes σ z gates acting on qubit i to act on qubit j.Due to the unitarity of the iSWAP operation, its action on a NN Hamiltonian evolution can be written as Therefore, the final Hamiltonian results in The initial vertex permutation defining the system's NN coupling was P = [1, 2, 3, ..., L].After the iSWAP operation, the permutation that defines our system is P' = [τ ij (1), τ ij (2), τ ij (3), ..., τ ij (L)].This approach is straightforwardly generalized to a system with arbitrary connections.This means that, after sandwiching with iSWAP gates a system with certain connections, it interchanges the ones that had the two qubits being affected by the iSWAP gate.In our case, since we will be dealing with systems represented by a Hamiltonian path, the iSWAP operation reduces to a transposition in the corresponding vertex permutation.
As the set of transpositions that our NN resource can implement, {τ i i+1 } for i ∈ [1, L − 1], is a generator of the symmetric group S L , we can obtain any desired permutation using the correct transpositions.This means that we can simulate the evolution of any system with couplings represented by a Hamiltonian path using as resource the system with NN couplings.For example, the Ising Hamiltonian that represents Fig. 1(c), which we will call H 1 , is just obtained using the following transformations For the sake of simplicity, we will define a sequence of transpositions to be The permutations defined in Eq. 2 can be composed in terms of two groups of sequences, where k and L refer to the permutation P k L we are building and the sequences have been labeled to make clear the order of application.That is, In Appendix A, we proof that these are indeed the groups of sequences needed to obtain the desired permutations of Eq. (2).Note that both groups of sequences commute between them.
Let us now show an example for the case of 6 qubits.In order to obtain the permutation P 3 6 from Fig. 3, we need to apply the transpositions defined in Eq. 10, which are G 1 (3) and G 2 (3,6).However, in the particular case of G 2 (3,6), . The circuit that implements this set of transpositions using iSWAP gates is shown in Fig. 3, where each column of iSWAP gates represents one sequence of transposition.
To sum up, in this section we have shown an algorithm that, using adjacent iSWAP gates and the NN Ising Hamiltonian as resource, is able to simulate the evolution of an ATA Hamiltonian for the case of an even number of qubits.Let us now simplify the circuit so that it requires the smallest possible amount of iSWAP gates.

IV. SIMPLIFICATION OF THE CIRCUIT
In this section, we will show an optimized version of the previously discussed circuit.Besides, we will also give a decomposition of the circuit in terms of ZZ gates, which will be useful later.
Since we now need to combine the set of Hamiltonian paths {P k L } to obtain the desired ATA evolution, it is possible to FIG. 3. Circuit that simulates the evolution of a Hamiltonian path with vertex permutation P 3 6 .Each of the surrounding columns of iSWAP gates is related with one of the sequences belonging to the groups defined in Eq. 10.
simplify the total number of iSWAP (U ) gates needed.The total circuit is described by the set of gates The final ATA evolution will be described as In Appendix C, we show the demonstration leading to this simplified circuit.In Fig. 4, we show an example of the simplification for the case of 6 qubits.Using Eq. 5, we can decompose the gates F (k, L) into a set of SQR and ZZ i,j (φ = g j t f ) gates acting on adjacent qubits.Grouping parallel ZZ ij gates naturally leads to a circuit which can be implemented using the DAQC protocol, as explained in the following section.An example for the case of 6 qubits is shown in Fig. 5.
We now take into account that k consecutive parallel set of iSWAP gates can be decomposed into a k + 1 analog blocks plus some SQR.Since the total number of F (k, L) for k ∈ [1, L 2 − 1] gates is L 2 − 1 and each one requires two parallel sets of iSWAP gates, we require a total of 3L 2 −3 analog blocks to generate these gates.We also need 3 L 2 − 2 analog gates to implement the F (0, L) set of gates and 3 L 2 − 1 analog gates to implement F L 2 , L .Moreover, we need L 2 analog blocks more evolving during a time t f .The total amount of inhomogeneous analog blocks needed is then 5L − 12.
In the following section, given a NN inhomogeneous Hamiltonian, we will derive an algorithm to simulate the evolution of an arbitrary NN inhomogeneous Hamiltonian efficiently, both in time and in the number of analog blocks.This is the last step before obtaining an algorithm to simulate an arbitrary inhomogeneous ATA Hamiltonian.

V. SIMULATING AN ARBITRARY INHOMOGENEOUS HAMILTONIAN
In this section, we will show an algorithm to simulate the evolution of an arbitrary inhomogeneous NN Hamiltonian under the paradigm of DAQC, employing a similar algorithm to the one shown in Ref. [14].In this case, our resource will be a fixed inhomogeneous NN Hamiltonian.The algorithm we use has the following three advantages over the one shown in Ref. [14]: (i) It works for an arbitrary number of qubits; (ii) It requires the minimum amount of analog blocks; (iii) It optimizes the time required for the simulation.
We will first need to notice that it is possible to selectively change the sign of any desired combination of couplings.This is done by surrounding some of the qubits with X gates.We represent the action of the X gates by colouring the corresponding qubits in the graph representation (See Fig. 6).In order to change the sign of the desired combination of couplings, it suffices to colour differently the qubits connected to the desired couplings.In Appendix B we prove that this can be done for a NN chain with an arbitrary length.In Fig. 6, we change the sign of all the couplings in (a) and the sign of just one coupling in (b).
We will now decompose a H NN (g j ) evolution during a time t f into a set of H NN (g j ) evolutions that have been evolving during a time t n each, b) ) is obtained by introducing the iSWAP gates that transform a NN Hamiltonian in the desired Hamiltonian paths.This gates are described by the group of transpositions defined in Eq. 10.The set of transpositions obtained with this equation is translated into a set of iSWAP/iSWAP † gates surrounding the NN Hamiltonian as discussed in Section III.In c) we simplify the circuit by making use of iSWAP iSWAP † = I.These are the set of iSWAP gates defined in Eq. 12, which lead to the circuit depicted in d).
where X j i is an X gate applied on the i-th qubit j-th times and f n (k) is a binary function that determines whether an X gate is being applied in the k-th qubit during the n-th analog block, yet to be determined.In the last step, we make use where M nj = (−1) fn(j)+fn(j+1) .This defines the following system of linear equations, FIG. 5.This circuit is obtained by replacing each iSWAP in Fig. 4 by the expression shown in Eq. 6, where each of the exponentials have been multiplied by the appropriated single qubit gates to transform them into ZZ interactions.Then, these interactions are gathered and expressed as evolutions of NN Ising Hamiltonians, characterized by the different couplings g and their evolution time t f .Each of this inhomogeneous Hamiltonian evolutions can be implemented using the DAQC circuit discussed in Section V.The SQR employed in this circuit are the Hadamard gate (H) and the gate R, defined as R = HSH where S is the phase gate.The matrix M has only ±1 entries.The interpretation of M nj = −1 is that during the n-th analog block, the j-th coupling changes the sign.From now on, we will only focus on the M matrix instead of the f n (j) functions.
We will now assume without loss of generality that the following conditions hold ∀j Without loss of generality, b j can always be relabelled and changed of sign to hold these inequalities.Under these conditions, we propose the following M ma-trix, After inverting this matrix (see Appendix D), Eq. ( 16) leads to the time intervals . Recall that t k = 0 means that we do not need the k-th analog block for the simulation.
Let us now prove that these solutions for t n imply the minimum amount of analog blocks and that the time required for the simulation is minimal.As, through Eqs.21 and 22, we are mapping the set of times {t n } L−1 n=1 to the values {b j } L−1 j=1 , we need at least as much different t n as b j .Indeed, suppose that b j = b j .We can relabel them such that j = j + 1.Then, from Eq. 21, we get that t j = 0, so the total number of analog blocks is reduced by 1.Another particularly relevant case is when b j = 0 for k different values, for which the number of analog blocks needed is reduced by k − 1.
The time required to simulate the desired H NN (g j ) is defined as t sim = L−1 n=1 |t n |.Note that we do not take into account the time required to implement the X gates since we are supposing that they are ideal digital blocks, instantaneous.However, we believe that the circuit will still be minimum in time as long as we can parallelize the application of these gates.In Appendix E, we prove that, under the constrains of Eqs.17, 18 and 19, min(t sim ) ≡ t min = |b 1 |t f .We also prove in Appendix E that our circuit requires a time t min to perform the simulation of an arbitrary inhomogenous Hamiltonian, being this the minimum time possible.
As an example, in Fig. 7 we represent the implementation of one of the analog blocks shown in Fig. 5 e), required for a set of iSWAP gates.More precisely, the depicted block is necessary for an iSWAP gate between the qubits 2 and 3 and an iSWAP † gate between the qubits 4 and 5.
It is noteworthy to mention that we require at least L − 1 analog blocks to simulate the evolution of an arbitrary inhomogeneous NN Hamiltonian.
Until now, we have shown an algorithm that simulates the evolution of an homogeneous ATA Hamiltonian using as resource an inhomogeneous NN Hamiltonian.Furthermore, it does so with O(5L 2 ) analog blocks, since we need O(5L) inhomogeneous analog blocks which can be simulated using O(L) analog blocks coming from the resource for each.
It is straightforward to modify the circuit in order to simulate an inhomogeneous ATA Hamiltonian with negligible impact on the performance.It suffices to change the blue blocks in the circuit of the Fig. 5 for an inhomogeneous Hamiltonian.
In order to implement this circuit for an odd number of qubits, L, we can use the same set of Hamiltonian paths, P k L , of Eq. 2. In this case k ∈ [1, L+1  2 ] and, in order to obtain an homogeneous ATA Hamiltonian, we need to set to zero some of the couplings used for the Hamiltonian path evolution representing P L+1 2

L
. It should be noted that the number of analog blocks will still O(3L 2 ).Even though we do not discuss here how to obtain the iSWAP gates for this case.Similar techniques to those discussed in Appendix A can be employed.

VI. CONCLUSIONS
We have shown that, within the DAQC paradigm, naturally arising evolutions can be utilized to simulate any inhomogeneous ATA Ising Hamiltonian along with SQR.In particular, we have designed an algorithm based on a NN Ising Hamiltonian with O(5L 2 ) analog blocks, where L is the number of qubits in the chip.For this, we also discussed both a digital approach that simulates an ATA system while having NN-like connections and an algorithm that simulates under the DAQC paradigm the evolution of an inhomogeneous Hamiltonian.This last algorithm has been proven to be efficient in the number of analog blocks and in the simulation time required, as long as we treat SQR as ideal gates.This protocol can be ex-tended to platforms described by different Hamiltonians, such us the XX+YY NN Ising Hamiltonian.FIG. 7. Implementation of the circuit discussed in Section V.The digital block implemented is used in the circuit of Fig. 5 to generate an iSWAP gate between qubits 2 and 3, in parallel with an iSWAP † gate between qubits 4 and 5.The analog blocks shown in the RHS of figure (a) represent the evolution of a NN system, where the sign of some of the couplings have been inverted according to Eq. ( 20).The different evolution times are determined by Eq. ( 21) and (22).In order to meet the constraints imposed by Eq. (17)(18)(19), the coefficients b1, b2, b3, b4 and b5 are equal to g 5 , respectively (we made the assumption that g4 > g2 and hence |b2| > |b4|).Since b4 < 0, we need to change g4 of sign in all the analog blocks, which is achieved by applying a X-gate in Fig. (a).The dashed lines in the analog block represent a coupling changed of sign.These dashed lines connects two qubits with different colour, whereas a solid line connects two qubits with the same colour.The change of sign of the i-th coupling is given by the i-th column of the matrix defined in Eq. (20).For example, the first column of the matrix, shows that all the signs of bj belonging to the first block must be inverted except from b1, which is related to g2.Consequently, all the signs of the couplings must be inverted, except from g2.In figure (b) we sandwiched each analog block with X gates in the qubits that where coloured, representing in that way the same evolution of figure (a).Lastly, in figure (c) we simplified the previous circuit both by eliminating all the analog blocks with zero time evolution, and all unnecessary X gates, taking into account that XX = I.
vertex permutation P k L and P k=1 L .Hence where it is straight forward to prove that F (k, L) has the form described in Eq .12 for k = 0 and k = L 2 .For k ∈ [1, L 2 − 1], we will prove that the set of iSWAP gates can be further simplified to obtain the Eq.12.

APPENDIX D: INVERSION OF MATRIX M
For the inversion of the matrix M of Eq. 20 it suffices to make row operations that transforms the M into the identity matrix while the identity matrix is transformed into M −1 .The required row operations are where r i refers to the i-th row, L is the number of qubits and hence L − 1 is the dimension of M .

APPENDIX E: MINIMUM TIME OF SIMULATION FOR ARBITRARY INHOMOGENEOUS NN HAMILTONIAN
In this appendix we will prove that the solutions obtained in Eq.21 give, under the constraints of Eq. 17, 18 and 19, the minimum value possible to t sim .This function is defined as (E1) We will first prove that min(t sim ) = |b 1 t f |.For that, recall that Eq. 15 defines the relation between b j and t n .Computing its absolute value, we obtain Using the constraints, we know that b 1 is the maximum value of b j ∀j.This proves that min(t sim ) = |b 1 t f |.The solutions obtained in Eq.21 hold that t k > 0 ∀k.We now compute t k = b 1 t f , which proves that this set of solutions makes t sim minimum.
Notice that, even thought the constraints may seem too restrictive, b j can always be relabelled or changed its sign in order to hold them.
FIG. 1. Examples of Ising Hamiltonians as their graph representation.Figure (a) shows a complete K5 graph, which represents a HATA(g) Hamiltonian for 5 qubits.Figure (b) shows a Hamilton path which represents a HNN(g) for 5 qubits.Figure (c) shows another Hamiltonian path with the vertex permutation P = [1, 3, 4, 2, 5].

4 FIG. 4 .
FIG.4.Simplified circuit simulating an ATA Hamiltonian evolution.Figurea) shows the three Hamiltonian paths that form the ATA evolution.Figureb) is obtained by introducing the iSWAP gates that transform a NN Hamiltonian in the desired Hamiltonian paths.This gates are described by the group of transpositions defined in Eq. 10.The set of transpositions obtained with this equation is translated into a set of iSWAP/iSWAP † gates surrounding the NN Hamiltonian as discussed in Section III.In c) we simplify the circuit by making use of iSWAP iSWAP † = I.These are the set of iSWAP gates defined in Eq. 12, which lead to the circuit depicted in d).

FIG. 6 .
FIG.6.Coloured graphs representing the surrounding of X gates in the evolution of a NN system for 5 qubits.A coloured node corresponds to a qubit surrounded by X gates.The dotted lines represent the change of sing in the coupling.Fig.(a) represents the inversion of all couplings, which is the same as inverting the time evolution of the system.Fig.(b) represents the inversion of only one of the couplings.