Design and cryogenic operation of a hybrid quantum-CMOS circuit

Silicon-On-Insulator nanowire transistors of very small dimensions exhibit quantum effects like Coulomb blockade or single-dopant transport at low temperature. The same process also yields excellent field-effect transistors (FETs) for larger dimensions, allowing to design integrated circuits. Using the same process, we have co-integrated a FET-based ring oscillator circuit operating at cryogenic temperature which generates a radio-frequency (RF) signal on the gate of a nanoscale device showing Coulomb oscillations. We observe rectification of the RF signal, in good agreement with modeling.

While silicon-based complementary metal-oxidesemiconductor (CMOS) technology constitutes the mainstream of electronics, research for the beyond CMOS era focuses mostly on devices relying on new materials and/or quantum features [1][2][3] . Although circuits can be made with these advanced devices, like graphene-based oscillators 4 or single-electron transistors (SETs) [5][6][7] , a first step is to interface these quantum nanoelectronic devices with conventional CMOS circuits. The integration with mainstream technology is greatly simplified when the novel device is silicon-based. Hybrid circuits using a small number of field effect transistors (FETs) and SETs have been demonstrated [8][9][10][11][12][13] . Recently an SET device has been integrated with CMOS 1-bit selectors 14 . In this work SETs working up to 300K were obtained by very small nanowire cross sections resulting in shape fluctuations. Here we demonstrate the integration of an SET relying on well controlled dimensions 15 and a ring oscillator (RO) CMOS circuit designed for low temperature operation, made with more than 600 FETs. The different FET or SET behaviour is obtained by varying the width of transistors all fabricated with the fully-depleted silicon-on-insulator (FD-SOI) nanowire technology 16 . The RO output feeds a non-overlapping clock generators which delivers two, phase shifted square wave signals at radio frequency onto the gates of the SET device. When the RF is turned on we observe a dc current in the SET at zero source-drain bias, due to rectification effect. This effect naturally arises when sufficiently large RF signals are applied to a non-linear device 17,18 .
A schematic diagram of the whole circuit patterned on a 11 nm thick SOI film with the trigate SOI technology 16 is shown in Fig. 1. The SET is made with a 25 nm wide nanowire covered by 2 gates of length 40 nm. Only one of the two gates is used in this study. The gate stack consists of ≈ 0.8 nm of SiO 2 , ≈ 2 nm HfSiON, 5 nm of TiN and 50 nm of polycrystalline silicon. After gate etching a single, self-aligned 12 nm Si 3 N 4 spacer is deposited. The back-end process follows with FIG. 1: Schematics of the whole circuit designed and fabricated on 300 mm SOI wafers. The nanowire dominated by Coulomb blockade below 10 K is on the right. The CMOS circuit driving the gates is made of several sub-circuits. A voltage controlled oscillator (VCO), monitored through a frequency divider, feeds a clock generator also based on ringoscillators. This generator delivers two delayed and phaseshifted RF signals, RF 1 and RF 2, which are further attenuated by capacitive dividers and added to external DC biases. The voltage supply VDD referenced to ground GN D is not shown. epitaxy for raised source/drain, doping and silicidation (NiPtSi). The circuit for generating RF signals is made with 2×1 µm wide channels and 60 nm long gates. All the transistors are supplied with a voltage V DD referenced to ground (GND). The circuit starts with a Voltage-Controlled Oscillator (VCO) made of 20 inverters and 1 NAND gate. A voltage controlled current source is inserted in the inverters with an N-type FET in footer configuration. The VCO can be switched ON or OFF with the OSC input and its frequency is tuned by an external control voltage VCO. In agreement with simulations the VCO output frequency ranges from 300 kHz (VCO=0.2 V) to 1.8 GHz (VCO=1 V) at 300 K. It feeds a second, non-overlapping clock generator with two outputs. It is made of 5 buffers allowing to shift by 108 ps the two signals, ensuring that only one of the two outputs is in the high (V DD ) state at any time. In addition the fre- quency of the VCO is monitored by a frequency divider. The two outputs RF 1 and RF 2 are attenuated by capacitive dividers in order to lower their amplitudes down to 0.5 mV, and they are added to two DC voltages DC1 and DC2 thanks to bias tees realized with 1 MΩ poly-silicon resistors. In the end DC1 + RF 1 and DC2 + RF 2 are respectively applied to gates 1 and 2 of the SET device.
The circuit implementation is shown in Fig. 2, with detailed views of the RO and SET. It uses 12 aluminium pads for external control (see Fig. 2a). The passive components of the circuits are the resistors (red squares) and the 2 pF and 1 fF capacitors (empty cyan squares in Fig. 2a) made between the two metal layers of the backend process. The RO and frequency divider are located between pads 3 and 4 (see Fig. 2a and 2b).
The frequency response of the VCO is shown in Fig. 3 for various temperatures. The RO being fed by the output current of the N-FETs controlled by VCO, we obtain a curve similar to the drain-source vs. gate voltage characteristics of an N-FET, with a sub-threshold regime getting steeper as the temperature decreases and a saturation at 1.36 GHz at 300K and 1.06 GHz at 4.2 K. This very good behaviour down to 4.2 K of a CMOS circuit containing 600 approximately transistors shows that conventional silicon electronics is perfectly suitable for use at low temperature, provided that passive components such as capacitors and mostly resistors are carefuly designed.
Because of its small cross-section the quantum device driven by the CMOS circuit exhibits Coulomb blockade oscillations below ≈ 10K 15,19 , as shown in Fig. 4a where the low-frequency transconductance G dif f versus the gate voltage which is varied (V g ) is shown at 1 K. Four quasi-periodic peaks are observed, corresponding to the addition of 4 electrons in the channel below the gate. The period of 18 mV in V g corresponds to an effective gate capacitance of 9 aF. These results are obtained without DC drain-source bias and no RF applied, hence there is no DC current flowing through the device in that case.
When the CMOS circuit is turned on, but still no DC bias applied, we measure a DC current, shown in Fig 4b. The presence of current in absence of bias and its characteristic dependence with V g is well explained by a rectification effect. In nanoscale devices which are by principle difficult to contact perfectly, AC signals driven onto gates can induce a parasitic oscillatory source-drain bias 17 . For electron pumping experiments it is important to discriminate between this spurious current and the true pumped current 17,18 . Following these previous studies, we consider an RF driven gate voltage V g (t) = V DC g + Asin(2πf t) which couples capacitively to the source and drain, hence creating an additional AC bias component at the same frequency f in addition to  the DC bias V DC ds : where k and φ characterize the coupling. The rectified current is the average over one period 1 f of the resulting current I(t) = V ds (t)G(t): As already pointed out in 17 and 18 , the general expression obtained by combining 1 and 2 is greatly simplified in the limit of small driving amplitude A. This is the standard case for AC lock-in measurements where one can use a linear approximation: Here we are interested in the integral over one period (equation 2) to get the DC component, hence the same approximation is used again and This model is used to calculate the rectified current I R in the general case and taking into account our nonsinusoidal RF excitation by using the Fourier series describing a square wave instead of a single sine wave. The results are shown in Fig 4c. We found an excellent agreement with the measurements (Fig 4b) and recover the result that I R is proportional to the second derivative of the conductance (equation 3). This is expected since we operate the circuit with RF output amplitude 500 µV, which is small compared to the Coulomb oscillations period in the transconductance. Indeed this amplitude is of the order of the linewidth of the graph in Fig 4a.

I. CONCLUSION
We have designed, fabricated and operated down to 4.2K a circuit allowing to generate on-chip RF signals on the gates of a nanoscale quantum device. The clock generators based on a ring oscillator as well as the capacitance divider and bias resistors are fully operational down to 1 K. We have observed a finite DC current through the quantum device in the absence of DC bias when the RF drive is turned on. This current which scales with the derivative of the differential conductance is well understood within the framework of rectification due to capacitive coupling of the gate signal to the source and drain of the nanodevice. These results pave the way for the integration of conventional CMOS circuits operating at low temperatures together with quantum devices. P. Clapera acknowledges support from the PhD program of the Nanosciences foundation in Grenoble. This work was partially supported by the EU through the FP7 ICT projects TOLOP (318397) and SiAM (610637), and by the Joint Research Project Qu-Ampere (SIB07) from the European Metrology Research Programme (EMRP). The EMRP is jointly funded by the EMRP participating countries within EURAMET and the European Union.