Tailoring potentials by simulation-aided design of gate layouts for spin qubit applications

Gate-layouts of spin qubit devices are commonly adapted from previous successful devices. As qubit numbers and the device complexity increase, modelling new device layouts and optimizing for yield and performance becomes necessary. Simulation tools from advanced semiconductor industry need to be adapted for smaller structure sizes and electron numbers. Here, we present a general approach for electrostatically modelling new spin qubit device layouts, considering gate voltages, heterostructures, reservoirs and an applied source-drain bias. Exemplified by a specific potential, we study the influence of each parameter. We verify our model by indirectly probing the potential landscape of two design implementations through transport measurements. We use the simulations to identify critical design areas and optimize for robustness with regard to influence and resolution limits of the fabrication process.


I. INTRODUCTION
Demonstrator devices for electron spin qubits have been shown to work with high manipulation [1][2][3][4][5][6][7][8][9] and readout fidelities [9][10][11][12] and indicate a possible path to scaling to a quantum computer [13][14][15][16][17][18].Gate-layouts of most demonstrator devices are closely related to or copies of previous devices of a research group or of published layouts.Their functionality has been mostly tested as completed devices and therefore only few iterations are made due to the relatively slow feedback cycle.Scaling up to larger qubit numbers requires optimized and new device layouts.As devices become more complex, testing of many device generations is not sufficient to achieve high yield and robustness to material variations.To this end, simulations are needed to predict functionalities and finally increase the feedback cycle from device measurement to fabrication.Simulation tools are extensively used throughout the advanced semiconductor industry for high complexity devices, as for example technology computer-aided design which is used for transistor, photo detector and miniature solar cell designs [19][20][21].
In contrast to these applications, spin qubit devices require the accuracy of single electron control, include tunnel barriers and are mostly based on smaller designs.These simulations require additional quantum mechanical constrains.Adaptions of the TCAD software allowing for quantum mechanical restrictions have been implemented with the focus on optimizing qubit distances for manipulation and tunnel couplings [22].There are simulation-based micro-magnet designs optimised for fast and precise spin manipulation by electric dipolar spin resonance [8,23,24].The coupling to electron reservoirs has been calculated by simulating the induced potential in * lars.schreiber@physik.rwth-aachen.dethe 2DEG and approximating the Hamiltonian [25,26].A detailed comparison to experimentally applied voltages has only been shown for gate pinchoffs [27].
These modelling efforts are based on ideal devices layouts.However, the consideration of process constrains promises higher functionality and device yields.To that extend, fabricational variations such as line-edge roughness on the order of a few new nanometers [28], and the limitations of patterning with electron beam lithography at non-vertical angles need to be considered [29].
Here, we present a general approach to electrostatic modelling of a targeted potential taking into account the gate structure, doping, reservoirs and applied bias.We consider the influence of fabricational variability to optimize for stability and few device iterations.For a specific targeted potential, implementations for both undoped and doped heterostructures as well as a depletion and accumulation mode designs are considered.For two different heterostructure implementations, the simulated functionality is ratified experimentally.

II. TARGET POTENTIAL
Our approach can be used to implement any targeted potential.To exemplify the possible application, we discuss one specific potential to highlight the studied parameters.For this example, the aim is to form a quantum dot (QD) that has identical tunnel couplings to source and drain reservoir, but a significantly larger capacitive coupling to the source than the drain reservoir (Fig. 1a).We implement this configuration by forming a QD potential with a sharp tunnel barrier to the source reservoir and the drain reservoir with an added potential section in between the second barrier and the drain reservoir.The potential in this added section, named slide, slowly decreases the potential to the chemical potential of the drain reservoir over a distance of several 100 nm (Fig. 1b).This specific potential is studied as a QD charge sensor with enhanced performance [12].A double quantum dot (DQD) is added next to it, which can host the spin qubit.The capacitive coupling between the QD of the sensor and the DQD must be high for good charge sensitivity.

III. GATE LAYOUTS
To highlight the versatility of our simulation approach regarding the heterostructure and the charge accumulation, we choose three different realization, including both a doped and an undoped heterostructure as well as a depletion-and an accumulation-mode design.A depletion-mode design requires a filled two-dimensional electron gas (2DEG) and depletes the QD regions to the few electron regime and has been studied for both doped [30][31][32][33][34] and undoped [1,3,35,36] heterostructures.In the later case, the lack of doping of the 2DEG is compensated by a global top-gate, to which a positive voltage is applied for accumulating charge carriers in the 2DEG.Therefore, on the one hand the gate voltage applied to this global top-gate determines the electron reservoir accumulation, but at the same time it influences the potential in the QD region.This lack of tuning flexibility is often problematic.The problem is solved by an accumulation-mode layout: This is a device with multiple pattern gate-layers, for which positive and negative voltages for accumulation and depletion are chosen within layers [2,[37][38][39][40].
We built a finite-element model of a doped GaAs/AlGaAs and undoped Si/SiGe heterostructures with simplified layer stacks in regards to the permittivity of the different materials (Fig. 1c,d) as the basis of the electrostatic simulations.For the GaAs/AlGaAs devices, the depletion gate layer is added directly on top of the heterostructure as metal surfaces.The Si/SiGe devices include an oxide layer underneath the depletion gate layer and between metal gate layers.For the multi-gate layer accumulation design, oxide layers and metal gate layers are alternated.The quantum wells are implemented as a two-dimensional layer within which charges can be accumulated according to the Thomas-Fermi approximation (see Appendix A) [41,42].We perform the electrostatic simulation using the finite-element solver COM-SOL Multiphysics (simulation parameters in Appendix B) and determine tunnel-barriers by Wentzel-Kramers-Brillouin (WKB) approximation.
We realize the potential for three different boundary conditions: (I) a doped GaAs/AlGaAs heterostructure (II) an undoped Si/SiGe heterostructure with a global topgate and (III) an undoped Si/SiGe heterostructure with an accumulation mode design.Next to the sensor, a DQD is formed in the QW by properly shaped metal gates.For the GaAs/AlGaAs implementation (I, Fig. 2a) the targeted potential is formed by three additional gates added to the sensor design (marked red in Fig. 2a).The angle and shape of which are adjusted in the simulation.
In the slide region the potential is depleted without generating a barrier.As the optimal path is nontrivial, the Dijkstra's algorithm (see Appendix C) is used to find the optimal path through the tunnel barriers of the sensor and the slide potential (Fig. 2b).The charge density shows that due to the applied bias V SD = 10 mV the 2DEG in the slide region is depleted.
One Si/SiGe implementation (II, Fig. 2c) uses similarly to the previous case a gate on top of the slide and two side gates (marked red in Fig. 2c).All three gates are set to positive voltages.The side gates have a small angle α between each other to ensure a widening potential.The potential line cut through the sensor and corresponding charge density show the targeted slide potential depleted from charge carriers according to the negligibly small charge density ρ (Fig. 2d).
The second Si/SiGe implementation uses an angle in the confinement gates and a separated accumulation gate in the slide region to define the potential (III, Fig. 2e,f), as shown in the gate structure separated into metal layers (Fig. 2g-i).These simulations allow us to optimize the gate layout without fabricating each design while adhering to the fabrication limitations.For each realization, we are able to judge the feasibility of tuning the voltages applied in each layout to generate the targeted potential.Especially, regions with nontrivial cross-coupling from individual gates (mainly non-orthogonal gate structures) can be studied and optimized to fit a specific potential.Therefore, problems such as required unrealistic fine tuning of specific gates can be avoided.

IV. BENCHMARK SIMULATIONS BY EXPERIMENTS
A. Capacitive coupling to sensor QD After modelling these very different design layouts, it is indispensable to confirm our simulation methods.To ratify our simulations, we fabricate and test the last design iteration.While the potential is the obvious parameter extracted from the simulations, direct probing of the potential shape for the entire device is hardly possible.Instead we limit ourselves to benchmarking specific measurable properties related to the targeted potential.As an alternative measure, we choose the capacitive coupling of the drain reservoir C D to the sensor QD for this specific application, which can be extracted from both the simulations and transport measurements.C D allows us to indirectly probe parameters of the specific underlying potential landscape.Simulations of other device layouts can require an adjusted probing measure, with possibilities being calculated and measured tunnel couplings or relative lever arms of different gates among others.C D can be extracted from the simulations, by varying the bias V SD applied between the reservoirs and extracting the leverarm of one reservoir on the QD potential (see Appendix D).
On the experimental side, measuring a QD in transport formed in the targeted at potential (cf.Fig. 1) leads to strongly tilted Coulomb diamonds [12] from which C D can be measured.A large and continuously declining slide region decouples the drain reservoir.This decoupling leads to a large negative Coulomb diamond slope m, while the positive slope (m + ) remains nearly constant.
We correlate the slope m to the capacitive coupling C D between the drain reservoir and the QD, via the coupling asymmetry η to source and drain reservoir: where V PS is the voltage applied to the QD plunger PS, C PS and C Σ are the capacitive coupling of the gate PS and the total capacitive coupling of all gates, respectively.
To probe the potential, we vary the applied gate voltages in the slide region and extract the slopes of the Coulomb diamonds measured for various voltage configurations.
For the case II, Si/SiGe with a global accumulation gate, we measure this experimental dependence.
A device similar to the tested one is depicted in Fig. 3a.The voltage of the marked gate SR is adapted to change the potential of the sensor region and control the coupling to the drain reservoir, while the gate PS and the bias applied between the ohmics V SD are used to measure the diamonds.For larger values of V SR , the standard Coulomb diamonds (Fig. 3b) are measured and the negative slope m of the diamond is extracted.The diamond tilt is enhanced for a decreased voltage applied to gate SR.A steep negative Coulomb diamond slope m is observed for a very low voltage V SR (Fig. 3c).Comparing m for different slide configurations reveals a systematic decrease in m as a function of a decreasing voltage applied to SR (Fig. 3d).This corresponds to a formation of a slide region after the second barrier which is elongated as lower SR values narrow the path to the drain contact.
The device layout is optimized for an η = 200 by simulation.Note that larger asymmetries parameterized by η are possible according to the simulation, but are of limited use as the corresponding tuning of the plunger voltage applied to gate PS needs to be as accurate as ∆V PS =0.5 mV to use the QD as a sensor.The maximum value obtained experimentally during a separated measurement on second sample is η=85.The discrepancy between the simulation and experiments can be attributed to imperfect gate structures or defects as both required an adjustment of the applied voltages, which will shorten the length of the slide region.
Via this indirect probe, we can measure a few aspects of the potential, such as verifying the tunnel barriers and the formation of a tunable slide region.Even without a general or global potential probe, we can ratify our simulation assumptions.

B. Influence of reservoir bias
Essential for accurately modelling the potential landscape is not only a description of the gate layer influence, but also a good description of the impact of the electron reservoirs and the applied bias V SD between the source and the drain reservoir of the sensor.The extend of the reservoirs determines the reach of the screening effects of accumulated electrons.A change in V SD has a large influence on the overall potential landscape and changes the size of reservoirs.For complex gate layouts and bias V SD electrostatic landscapes, the extend of the reservoirs is non trivial and can only be predicted by simulations.
To study the bias V SD influence, we exemplary use a device similar to case I (Fig. 2a), a doped GaAs/AlGaAs device, which was optimized for larger bias values.A device identical to the one measured and simulated is depicted in Fig. 4a.For this layout, simulations with varying bias voltages V SD are performed without changing the gate voltages in between (Fig. 4b).The bias V SD is applied asymmetrically, meaning that only one reservoir potential is shifted.The length of the slide region is determined by the applied V SD as the reservoir moves into the slide region for low V SD .The boundaries of the reservoir can be identified by the charge carrier density.We experimentally verify this simulation of the bias impact by comparing to the measured Coulomb diamonds of the device.As discussed for Fig. 3, the extracted capacitive coupling C D is used as the probe for the potential shape.For large bias voltages V SD , the Coulomb diamonds tilt even for a QD, which has nearly equal capacitive coupling between sensor QD and its source and drain reservoirs, respectively.We name this type of SET, which does not employ a slide potential, a symmetrically-coupled QD.
Here, the asymmetry arise due to a large bias V SD applied only to one of the two reservoirs.As this device is based on a doped heterostructure, measuring the device with no voltage applied to the gate DB5 allows for the use as a symmetrically-coupled QD.We extract the slope m of the Coulomb diamonds as a function of the bias V SD (Fig. 4c).The absolute value of the slope increases with the applied bias V SD .
An asymmetrically coupled QD can be formed, when depleting the slide region by the voltage applied to gate DB5, forming a potential as intended in the simulations (cf.Fig. 1b).Then, steeper diamond slopes are observed (Fig. 4d).With an added slide region to the potential, the increase of the slope's m absolute value with an increasing bias V SD is significantly larger, as expected from the simulations, where the slide length and therefore the capacitive coupling of the drain reservoir to the QD strongly depends on the value of the V SD applied (inset Fig. 4d).The experimentally observed larger tilt of the Coulomb-diamonds (Fig. 4c vs d) is correctly predicted by our simulation.

C. Fabricational variability
A significant benefit of simulating different layouts is the possibility to find a robust design with regard to fabricational influences and imperfections.Therefore, we analyze the stability of the simulated gate-layouts with regard to the spatial resolution limit of the nanolithography of the metal gates.Exemplary for the geometry of device type II (cf.Fig. 2c), we first study the impact of the line-edge roughness of a patterned gate structure.The edges of the metallic gates of an exemplary device are identified by applying shape recognition on a scanningelectron micrograph (Fig. 5a).The observed realistic line-edge roughness is fed back to our finite-element device model to predict its impact on the targeted potential shape.The calculated potential along the optimal path predicts a slide potential with multiple ripples after fine tuning the voltages applied when using the realistic lineedge roughness in contrast to the perfect gate edges (Fig. 5b).Although the general potential is obtained, we note that a shorter slide region than compared to the ideal gate-layout is likely to occur as the voltages are tuned to form only one QD with two sharp barriers.
Note that in general it is even not required to fabricate an exemplary device.A simple variation of the shape of the metal gates in the simulation is sufficient to study the robustness to fabrications imperfections.In addition to line-edge roughness [43], limitations to accurate alignments of nano-lithography [44] can be explored by simulation.Non-orthogonal and especially small angled gate structures are not fabricated accurately when relying on electron beam lithography [29,45].To quantify its impact on the generated potential, we implement small change in angles of the gates in our finite-element model.As an example of angle variation, the position of the corner of the gate labelled SR is changed along the y-axis.This results in variations of the opening angle of the gap between the gates in the slide region (bright blue dot Fig. 5a).For a few nanometers' displacement, our potential simulation predicts that the potential slide is reduced to half its original length or that a flat potential region might occur (yellow and blue line in Fig. 5c, respectively).In the first case, a significantly lower asymmetry η would be experimentally obtained causing a decrease in sensor gain [12].In the second case the sensor current might be blocked, since the potential disorder (cf.Fig. 5b) alters the flat potential region into a series of disordered QDs and possibly block the current through the sensor region.
Tuning the voltages applied to specific gates can partly improve the shape of the potential.Also this tunability can be predicted by our device model: For the case of -10 nm displacement, the tunability of the slide with respect to the V SR voltage is shown in the inset of Fig. 5c.Tuning the voltage dominantly alters the height of the potential within the slide region and therefore has a small influence on the linear slope of the slide.Our discussions show that gate-layouts, which are unreliable with respect to fabrications imperfections, can be studied and the impact of these imperfections can be eliminated by simulation.
We conclude with a final example of simulationsupported gate design, which has motivated our choice to use the thin metal gate in the device type II (Fig. 5a).For this purpose, we compare a summarized and simplified Si/SiGe device-layout (inset Fig. 5d) of a sensor without a capacitivly coupled DQD.Similar to device type II, we include a global accumulation gate in our device model.The simplification to a symmetric single dot without a DQD nearby allows us to reduce the input parameters.Electrostatic simulation of the variation of the angle of the slide forming gates (cf.Fig. 5c) reveal a larger influence on the slide potential shape (Fig. 5d): A second unintentional potential minimum emerges in the optimal path.
The larger influence of variations in the simple device than the case II device (Fig. 2c) can be understood by our simulations as well: It is caused by the electric field gradients at the quantum well (Figs.5e,f).For the device type II, the simulated potential forms a single minimum at the height of the quantum well (grey scale Fig. 5e, where a little center gate is included).However, the electric field is mainly defined by the gates patterned on the depletion gate layer while the accumulation gate influence is blocked by the central gate along the current path (colorscaled arrows Fig. 5e).For the simple device without the central thin gate, the influence of the global accumulation gate dominates (Fig 5f).Both the electric field (color scaled arrows) and the potential (greyscale) strongly depend on the global accumulation gate.For both devices the gates in the depletion gate layer are tuned to have similar voltages to be less sensitive to variations.Thus, we conclude that the thin long gate in device layout II better screens the effect from the top-gate, which has larger potential difference compared to the difference of the slide gates within the depletion layer.For any aimed at design, the consideration of the generated electric fields is useful, as they indicate layout positions which are most impacted by small variations.As it is not possible to fully avoid fabricational fluctuations, reducing generated electric fields improves the robustness and leads to a higher yield.

V. CONCLUSIONS AND OUTLOOK
We show a general approach to electrostatic modelling of spin qubit devices.Our model includes descriptions of the heterostructure, gate layers, reservoirs and applied bias and can be applied to accumulation or depletion type heterostructures.We show gate-designing by device simulation for an exemplary targeted potential shape, which is rather demanding.We experimentally benchmark our simulation by probing predicted gate-voltage dependencies of current through the device.By simulating our device layout, we were able to predict the properties of and successfully operate first generation devices [12].We included a study to make the gate layout robust to unavoidable fabrications imperfections.With our general finite-element modelling of qubit devices, the electrostatic potential landscape can be predicted and the gate-layout optimized without the need of resource-costly fabrication iterations.not represent the quantum mechanical behavior of the electron.

Appendix D: Capacity extraction from simulation
The coupling asymmetry η depends on the capacitance ratio C Σ C −1 D .The potential of the dot depends linearly on the voltage applied to the drain reservoir V SD with the factor α D = −C D C −1 Σ .This was extracted from the simulations by varying V SD and monitoring the potential minimum V 0 .η is then given by This was realized by running the simulation for a specific design nine times with varying V SD = -10 mV + [-1 mV, -0.75 mV, -0.5 mV, -0.25 mV, 0 mV, +0.25 mV, +0.5 mV, +0.75 mV, +1 mV].The potential minimum was determined for each simulation by placing an ellipse around the dot and evaluating the potential on each mesh point inside.As the potential was only evaluated on the points of the discrete mesh, the element density was set accordingly to ensure a high enough resolution to cover possible shifts in the spatial position of the potential minimum.The so obtained potential minima were then plot-ted against V SD and fitted to obtain α D as shown in Fig. 6.

FIG. 1 .
FIG. 1. Parameter Settings.a Targeted coupling of a QD (blue) to source (S) and drain (D) reservoir.The tunnel couplings are identical, TS=TD, and the capacitive coupling of the dot to the drain is significantly smaller than to the source, CD CS. b Schematic potential matching the requirements in panel a.The tunnel coupling and capacitive decoupling is defined by the potential in section I and II, respectively.c,d Simulation input parameterization for Si/SiGe and GaAs/AlGaAs heterostructures, respectively.

FIG. 2 .
FIG.2.Modeled electrostatic potential.a Potential realization for a doped GaAs/AlGaAs heterostructure.The gate structure (black) and the optimal path (white) are indicated as well as the sensor QD and DQD regions (dashed orange).b Line cut of potential V (blue) and charge carrier density ρ (green) along the optimal path for the realization in panel a.The source and drain levels are indicated (black dashed).c Potential realization for an undoped Si/SiGe heterostructure with a global top gate.d Line cut of potential and charge carrier density along the optimal path for the realization in panel b. e Potential realization for a closed-gate design in an undoped Si/SiGe heterostructure with the first gate layer (black).g-i Stacking of layers one (yellow), two (blue) and three (purple) of closed gate design.

FIG. 3 .
FIG. 3. Experimental slide variation.a Scanning electron micrograph (SEM) of an identical device with marked slide gate (SR), plunger (PS) and sensor dot Ohmic contacts (crosses).b,c Coulomb diamonds with marked slope m for VSR = 0.35 V and VSR = 0.24 V, respectively.d Coulomb diamond slopes (blue) and η (green) in dependence of slide gate voltage.

FIG. 4 .
FIG. 4. Bias Influence.a SEM of an identical device with marked slide gate (DB5) and sensor plunger (DB2).b Simulation of bias influence on the formed potential.Only increasing the bias voltage, the slide length of the induced potential V (solid line) increases.Accordingly, the charge density ρ (dashed lines) extends into the slide region depending the applied bias.The beginning of the drain reservoir is marked with red arrows.c Coulomb diamonds of SET operation with asymmetrically applied bias voltage.The slopes (white lines) of the Coulomb diamond are extracted in the dependence of the applied bias.A current level of 1.5 nA is used as a threshold.For clarity, the low bias regime is depicted as an inset.To realize the SET operation, the slide forming gate voltage VDB5 is set to zero.d Coulomb diamonds of ASD operation with VDB5=-0.31V.For the same current threshold I = 1.5 nA, the slopes m(white lines) are extracted.The extracted m for both operation modes are depicted in the inset in dependence of the applied bias.

FIG. 5 .
FIG. 5. Potential robustness.a SEM of an indentical device.The edges of the fabricated gates (yellow) are extracted by image processing.b Potential line cut along optimal path using the gate edges (panel a) of a fabricated device (blue) and optimal gate edges (green).cInfluence of slide angle on optimal path potential.The slide angle is varied by changing the y position of the slide endpoint (blue dot panel a).The inset shows the compensation by slide voltage tuning for ∆y = −10 nm.Starting from the top ∆VSR,i = (i − 1) • 10 mV.d Slide angle influence for a simpler device (layout in inset).e Cross section of slide potential and electrical field perpendicular to the path at the position marked in red in panel a.The gate edges are marked in orange and the quantum well (red arrow) is placed at z=-45 nm.f Simple device cross section of slide potential and electrical field perpendicular to the path at the position marked in red in the inset of panel d.

FIG. 6 .
FIG. 6. Determination of the gate lever-arm αD by simulation.a Potential line cut along optimal path for bias voltages VSD.b Change in potential minima ∆V dot , obtained from an interpolation in the QD region of the 2D data of the potential linecuts in panel a, as a function of the change in bias voltage ∆VSD.The data points are linearly fitted to obtain the slope αD (green).