Measurement-free fault-tolerant quantum error correction in near-term devices

Logical qubits can be protected from decoherence by performing QEC cycles repeatedly. Algorithms for fault-tolerant QEC must be compiled to the specific hardware platform under consideration in order to practically realize a quantum memory that operates for in principle arbitrary long times. All circuit components must be assumed as noisy unless specific assumptions about the form of the noise are made. Modern QEC schemes are challenging to implement experimentally in physical architectures where in-sequence measurements and feed-forward of classical information cannot be reliably executed fast enough or even at all. Here we provide a novel scheme to perform QEC cycles without the need of measuring qubits that is fully fault-tolerant with respect to all components used in the circuit. Our scheme can be used for any low-distance CSS code since its only requirement towards the underlying code is a transversal CNOT gate. Similarly to Steane-type EC, we coherently copy errors to a logical auxiliary qubit but then apply a coherent feedback operation from the auxiliary system to the logical data qubit. The logical auxiliary qubit is prepared fault-tolerantly without measurements, too. We benchmark logical failure rates of the scheme in comparison to a flag-qubit based EC cycle. We map out a parameter region where our scheme is feasible and estimate physical error rates necessary to achieve the break-even point of beneficial QEC with our scheme. We outline how our scheme could be implemented in ion traps and with neutral atoms in a tweezer array. For recently demonstrated capabilities of atom shuttling and native multi-atom Rydberg gates, we achieve moderate circuit depths and beneficial performance of our scheme while not breaking fault tolerance. These results thereby enable practical fault-tolerant QEC in hardware architectures that do not support mid-circuit measurements.


I. INTRODUCTION
Implementation of quantum error correction (QEC) routines into inevitably noisy physical hardware is conjectured to be indispensable in order to enable large scale universal quantum computation [1].If errors on the quantum register that holds the logical information can be corrected faster than they occur, the threshold theorem guarantees that the computation can be continued for in principle arbitrary long times [2,3].Faulttolerant (FT) quantum circuits come with a qubit, gate or time overhead compared to non-FT circuits but can lead to lower logical failure rates provided the error rates of physical components are below a break-even point [4].For a QEC code capable of correcting t errors, any possible combination of t Pauli faults on all components 1 of a quantum circuit can never lead to failure of the circuit in order for the protocol to be fully FT.
Neutral-atom platforms are catching up quickly.The preparation of logical states of the Steane, surface and toric code has been demonstrated in an experiment with mobile atoms in optical tweezers [20].Proposals for FT quantum computing have been put forward that take into account specific aspects of this physical platform such as enhanced leakage errors [21,22] and first experimental observations were made recently [23,24].
Although most quantum computing hardware platforms are able to perform measurements of physical qubits, each have their own limitations that hinder straightforward application of QEC.In superconducting transmons for example, error rates of measurements are typically larger than error rates of physical gates and measurement crosstalk can affect neighboring qubits [19].In many hardware platforms, measurements are much slower than gate operations, leading to errors on qubits that are idling during measurement and feedback.In trapped-ion and neutral-atom platforms, this problem is exacerbated by the necessity of applying relatively slow laser recooling of ions after qubit detection [25] or laser cooling during detection to avoid atom loss [26].In trapped ion systems, alternative routes explore using different ion species for sympathetic cooling [27,28] or physical shuttling of ions into dedicated readout zones separated from the rest of the system to avoid heating of a large ion crystal [12,[29][30][31].In neutral-atom platforms, mid-circuit measurements have only recently been demonstrated [32][33][34]; however, they are still orders of magnitude slower than typical gate times on that platform.Real-time feedback based on measurements remains experimentally challenging but has been FIG. 1. Logical building blocks of the measurement-free fault-tolerant quantum error correction cycle.Errors on the logical qubit |ψ L are copied to a logical auxiliary qubit initialized fault-tolerantly in the appropriate basis.Then the a-bit syndrome is mapped from the logical auxiliary qubit (block S) to the second auxiliary block of a physical qubits.For each syndromecorrection pair, we repeatedly reset (R) the physical qubits to |0 , copy (C) the syndrome and apply the matching feedback operation Fσ of Pauli type σ ∈ {X, Z}.The repetition refers to all 2 a − 1 possible non-trivial syndromes.Instead of qubit reset, one may also supply fresh auxiliary qubits.The copy and feedback can be parallelized to avoid repetition and to reduce circuit depth and thereby the overall duration of the protocol if a larger number of physical auxiliary qubits is available (see Sec. II B).
Because of these challenges, there has been continuous effort in finding QEC schemes that circumvent the need of measuring individual qubits to obtain information about potential errors while at the same time maintaining fault tolerance.Note that some dissipative element is still needed for QEC to remove entropy from the system; either by the ability to reset qubits or to have a sufficiently large reservoir of fresh qubits [40][41][42].Autonomous quantum error correction protocols make use of engineered dissipation in a non-FT way [43].In bosonic codes it is common to engineer Lindbladians that have the code states as fixed points [44,45].Measurement-free EC need not be substantially inferior than conventional QEC in principle [46,47].A non-FT measurement-free surface code implementation has been shown in Ref. [48].Techniques to devise the T-gate and the Toffoli gate faulttolerantly without measurements were given in Ref. [49].In Ref. [50] a different measurement-free FT EC protocol was devised specific to the Bacon-Shor code while extendable to the class of Calderbank-Shor-Steane (CSS) codes.The authors proved a competitive threshold by means of concatenation for the 9-qubit Bacon-Shor code.QEC cycles can be implemented fault-tolerantly given additional assumptions about the form of the noise [51,52].However, devising practical measurement-free QEC schemes compatible with the number of qubits and native gate operations available in current quantum computers that incorporate full fault tolerance remains a challenging task.
In this manuscript we provide a QEC technique without measurements that is fully fault-tolerant towards circuit-level depolarizing noise on all circuit locations, inspired by Steane-type EC.We note that now logical qubit operations, i.e. initialization, Clifford gates and QEC cycles, can be implemented without the need of measurements and real-time feedback.In Sec.II we present our novel measurement-free FT QEC scheme, discuss resource requirements and compare the scheme to conventional flag qubit assisted QEC [53][54][55][56].Our scheme needs auxiliary logical qubit states, which can be prepared fault-tolerantly without measurements [57,58], as we show in Sec.III.In Sec.IV we provide protocols for practical implementations in state-of-the-art quantum hardware, via a) decompositions into two-qubit gates, b) native multi-qubit-controlled gates that were proposed for neutral-atom or ion trap architectures and c) multiqubit Mølmer-Sørensen (MS) gates native to ion trap quantum processors.Contrary to general folklore, using all these multi-qubit operations does not invalidate the FT property of the scheme if used at suitable positions in the QEC circuits.Moreover, we propose a shuttling schedule to implement the proposed scheme in a stateof-the-art neutral-atom quantum processor.We provide conclusions and an outlook on future work in Sec.V.

II. MEASUREMENT-FREE FT QEC CYCLE
Quantum error correcting codes are based on so-called stabilizer operators, whose eigenvalues must be measured in order to determine and correct for potential errors that might have happened to the logical qubit that is encoded in such a code [59].Two standard techniques to render QEC fault-tolerant are Shor-and Steane-type EC [60,61].The former verifies that a measured stabilizer expectation value is correct by fault-tolerantly encoding the syndrome into the parity of an auxiliary pre-verified FT GHZ-state.The readout procedure must be repeated until a majority vote determines the most likely value in order to protect against single measurement errors.With much fewer qubit and repetition overhead, the flag qubit paradigm was shown to efficiently realize FT QEC cycles [53][54][55].A small number of additional physical flag qubits act as heralds of errors that -with non-FT QEC -would lead to logical failure but can be corrected with flag-FT QEC.Measurement of syndrome and flag qubits FIG. 2. Detailed circuit on the physical qubit level of the measurement-free fault-tolerant quantum error correction cycle for the Steane code.The syndrome mapping (orange) does not require a distinctly FT routine because we perform intermediate reset operations R to the state |0 that erase potentially dangerous faults.The control-qubits of the feedback gates (green) are conditioned on the physical qubits being in the |1 (|0 ) state for a black (white) circle.Any suitable procedure to prepare the logical auxiliary qubits fault-tolerantly can be used.We provide a measurement-free FT initialization circuit in Fig. 6.For the last correction operation, copying from the third to the second block can be omitted.One can verify that no single error of any type on any circuit element will lead to an uncorrectable error.(a) X-correction block.A single bit-flip error on the logical data qubit, say X6 (red star), is propagated to the logical auxiliary qubit.The sixth physical CNOT gate propagates the fault as illustrated by the two subsequent red X markers.For a Z-fault, the propagation would happen reversely from the target to the control qubit of a CNOT gate.Propagation of Y -faults can be viewed as simultaneous occurrence of X-and Z-faults.Then, the syndrome is mapped to three physical qubits and copied to all multi-qubit-controlled feedback gates.The error is corrected by the second C3NOT gate.For the first and all other C3NOT gates the syndrome does not match the control structure.Thus, they have no additional effect on the logical data qubit.Note that, in contrast, for standard Steane-type EC, one would correct X6 by measuring all qubits of the logical auxiliary qubit in the Z-basis after the logical CNOT gate and applying the feedback conditioned on the measurement result.(b) Z-correction block.As required for an FT circuit, single faults within the auxiliary system can never cause more than a weight-1 error on the logical data qubit.As an example, we show the single fault event Z12Z16 (blue stars), which propagates to a correctable weight-1 error on the logical data qubit through the last C3Z gate.
is combined with classical processing and feedback conditioned on the in-sequence measurement information and, possibly, additional stabilizer measurements.This technique can be used in any QEC code.Steane-type EC on the other hand can be applied to the class of CSS quantum codes [62], which includes the well-known surface code [63,64] and two-dimensional color codes [65][66][67][68].
Steane-type EC sequentially corrects one type of Pauli errors (first X then Z or vice versa) by mapping faults from the data qubit register to a logical auxiliary qubit in the state |+ L or |0 L respectively.It then uses appropri-ate logical measurements of the logical auxiliary qubits to infer the most likely error on the logical data qubit, which can then be corrected by conditioning the classical recovery operation on the measurement outcome of the logical auxiliary qubit.
We demonstrate that with sufficient qubit and gate overhead the need for measurements in Steane-type EC can be circumvented.In the following we first lay out our scheme for a general distance-3 CSS code and the [ [7,1,3]] Steane code [69] -the smallest representative of the family of two-dimensional color codes [65][66][67][68] explicitly.We then discuss resources needed for implementation.Lastly, we demonstrate in which parameter regime we can expect an advantage of the scheme over conventional syndrome-measurement-based QEC.

A. Scheme
We illustrate one measurement-free FT QEC cycle of our protocol with logical building blocks in Fig. 1.It requires three qubit registers: the first holds the logical data qubit formed of n physical qubits, which we aim to correct, in an arbitrary logical state |ψ L , potentially having suffered from some fault.The second register of equal size is used to initialize a logical auxiliary qubit, analogous to Steane-type EC, in the state |+ L (|0 L ) when correcting X(Z)-errors.The third register contains a unencoded physical qubits which are all initialized to |0 (|+ ) when correcting X(Z)-errors.Our goal is to propagate faults, which are potentially present on the logical data qubit, through the circuit while at the same time preserving the logical qubit state during fault-free operation.In order to correct for X-errors on the state |ψ L , a transversal, i.e. bitwise, CNOT gate propagates them to the logical auxiliary qubit first as marked by the yellow block in Fig. 1.For two logical qubits both encoded in the same CSS code, bitwise application of physical CNOT gates between their physical data qubits implements the logical CNOT gate.Transversal gates are naturally fault-tolerant since there are no couplings between two qubits of the same block.Thus, a single fault on one logical qubit or a physical CNOT gate can never propagate to an uncorrectable error on any logical qubit.Since |+ L (|0 L ) is the state on the target (control) of the logical CNOT when correcting X(Z)-errors, there is no backaction on the control (target) state where we hold |ψ L .This way, one does not learn about the logical state itself since no expectation values of logical operators are mapped to the logical auxiliary qubit but only individual faults.Then follows a coherent syndrome mapping S from the second to the third register.The mapping can be done without special treatment to ensure fault tolerance, for example preventing uncorrectable errors on the logical auxiliary qubit, since the second register is anyways reset (R) afterwards.As a last step, the syndrome is coherently copied (C) back from the third to the second register and the feedback operation F applies the correction on the data qubit in the first register that matches the syndrome.This last step needs to be repeated for all syndrome-correction pairs.Subsequently, the analogous procedure is applied to correct for Z-errors with the previous X-and Z-type states and operations interchanged.An additional step of Hadamard gates on the a auxiliary qubits transforms the |+ states needed for the syndrome mapping to Z-eigenstates for the controlled feedback operation.
As an illustrative application example, we demonstrate our scheme using the [ [7,1,3]] Steane code.Our scheme is equally applicable to the distance-3 surface code [63,70], for which the treatment of single-qubit errors is analogous and we discuss the treatment of higher-weight errors in App. A. These two codes are the smallest instances of the leading approaches towards practical topological QEC.For the surface code, FT state preparation has recently been realized without measurements in Ref. [58].The Steane code allows one to encode k = 1 logical qubit in the code space as defined as the joint +1 eigenspace of the six stabilizer generators on n = 7 physical qubits as shown as part of Fig. 2a.The logical operators of the Steane code can be chosen as X L = X ⊗7 and Z L = Z ⊗7 .The Steane code can correct t = 1 arbitrary Pauli error and thus has distance d = 3.For a logical measurement after the QEC cycle, all physical qubits can be measured transversally (and thus fault-tolerantly).
The detailed circuits are depicted on the physical qubit level in Fig 2 .Here we remark that each data qubit correction is conditioned on its distinct three-bit syndrome, which is encoded into the control pattern of the C 3 NOT (or C 3 Z) gates that perform the corrections.Since the repetition for each data qubit correction starts by resetting the second register, the syndrome information can be copied anew from the third register using -in this example -a = n−k 2 = 3 transversal CNOT gates without breaking fault tolerance.The feedback operations are quasi-transversal in the sense that a distinct syndrome is uniquely connected to a single physical data qubit.Due to the reset operations there is no connection between the individual syndromes.Consider, for example, the error X 6 in Fig. 2a.It will be mapped to the three-qubit state |101 in the third register and, as a consequence, only the second C 3 NOT gate with the 101-control structure will act non-trivially on the logical data qubit and correct the error.As long as only a single fault occurs on the second or third register, at most one (potentially erroneous) correction operator is applied to the first block.The input state |ψ L is assumed fault-free when a fault happens within the cycle because the scheme is FT towards a single fault only.This resulting single error on |ψ L will always be correctable by the QEC code.If |ψ L already carries a single error, it is guaranteed by the then faultfree QEC cycle that the correct syndrome is mapped to the third register and the appropriate correction is applied.Two faults are necessary to cause failure of the protocol but a single fault can never cause failure because of fault tolerance.Assuming a physical fault rate p, the probability of failure is of order p 2 while for a non-FT protocol the probability of failure is of order p.
Note that we only required that transversal CNOT operations between the first and second block (to propagate the errors) as well as between the second and third block (to coherently copy the syndrome) are available.The FT auxiliary qubit initialization, syndrome mapping and feedback can be implemented with any routine that is most suitable for the particular hardware under consideration.Possible implementations into a neutral-atom tweezer array and an ion trap are sketched in Fig. 3, which we elaborate in more detail in Sec.IV.

B. Resources
The scheme as presented in Fig. 2 requires 2n physical qubits for the two logical qubits and a qubits to store the syndrome of one Pauli type.In total N = 2n + a = O(n) physical qubits are needed for an [[n, k = 1, d = 3]] CSS code.If the X-and Z-syndromes have the same length, as for color codes or surface codes, we can take the number of syndrome qubits to be a = n−k 2 .Note that some additional physical qubits might be required for the FT initialization of the logical auxiliary qubits depending on the specific code under consideration.The time overhead that is needed in order to perform the 2 a −1 feedback operations can be transformed into a qubit overhead, which is useful e.g. if the cycle time would be too long to implement the repeated copy steps or when no reset operation is available.Instead of repeatedly applying resets we can coherently copy the syndrome 2 a − 2 times to fresh auxiliary qubits.In this case the total number of qubits would increase to 2 ) because we still need two logical qubits using n physical qubits each but then we also need 2 a −1 blocks of a qubits each to connect each feedback operation to a distinct syndrome block.
Let us now count the number of CNOT gates that are needed to implement one QEC cycle, assuming for simplicity that the X-correction block and the Z-correction block are symmetric and thus require the same number of CNOT gates.Each logical CNOT gate amounts to n physical CNOTs.Then, a × s CNOTs are needed for the syndrome mapping step where we assume, for simplicity, that all stabilizers have the same weight s, i.e. the number of physical qubits that the stabilizers act non-trivially on.Coherently copying the syndrome 2 a − 2 times requires a bitwise CNOT gates each.We need m = 2 a+1 − 3 two-qubit gates to exactly decompose a single a-qubitcontrolled feedback operation targeting a single physical data qubit [71].For all 2 a −1 feedback operations we need m CNOT gates each.Therefore, in total, we require at most 2×(n + a(s + 2 a − 2) + m(2 a − 1)) CNOT gates to implement the QEC cycle.
It is desirable to reduce the circuit depth of the QEC cycle as much as possible due to the limited coherence times in near-term devices.If CNOT gates can be executed in parallel, the transversal CNOT gate can be run in just one time step, the stabilizer readout needs s time steps (again assuming all stabilizers have the same weight) and copying the syndrome from one block to 2 a − 1 blocks can be done in a time steps.All feedback operations can in principle be executed in a single time step if the physical architecture permits.
For the Steane code, these requirements amount to a total of 256 CNOT gates with n = 7 physical qubits, a = 3 stabilizers of each type that have weight s = 4.We elaborate a simplification of the multi-qubit-controlled gate decomposition in Sec.IV that will allow one to reduce m from 13 to 8 and thus realize the Steane code QEC cycle with 186 CNOT gates.In total, the minimum circuit depth that can be achieved with the Steane code is 2 × 9 = 18 as shown in Fig. 4. Note that furthermore the X-and Z-type correction part of the QEC cycle (see Fig. 2a and 2b) could also be largely carried out in parallel if one disposes of two simultaneously operated logical auxiliary logical qubits and registers of additional bare physical qubits.
Let us remark that the a physical auxiliary qubits are not strictly necessary to map the syndrome from the logical auxiliary qubit.Instead one may use an appropriate decoding circuit to obtain the syndrome on a subset of the physical qubits forming the logical auxiliary qubit and perform the quantum feedback as we discuss in more detail in App.B.

C. Measurement-free advantage
In the following, we analyze under which conditions the measurement-free (MF) EC protocol can be expected to yield lower logical failure rates than conventional EC involving syndrome measurements (SM).We provide an analytical estimation for advantageous use of the MFEC scheme and compare it to numerical statevector simulations.
We assume that all operations, i.e. gates, qubit initializations and measurements, in the circuits of the protocol, compiled into CNOT gates, are prone to depolarizing noise of strength p (see App. C for details on the noise model).Also, we consider an idling error rate p idle,m for idling during measurements for the measurement-based FIG. 4. The X-correction block of the measurement-free FT QEC scheme can be scheduled in nine time steps (dashed vertical lines) when parallel gate operations and N = 2 × 7 + 3 × (2 3 − 1) = 35 physical qubits are available.In the first step, the logical CNOT is applied.Then, from time step 2 to 5, the syndrome is mapped to a fresh set of auxiliary qubits.From time step 6 to 8, the syndrome is copied six times.In the last time step, the seven feedback operations are applied.It is possible to parallelize the Z-correction block analogously.
protocol and an idling error rate p idle,op for idling during operations for the MFEC protocol.These are the two dominant sources of idling noise for both protocols, assuming that the time to perform a qubit measurement is much longer than the time to perform a gate operation or qubit initialization/reset.The finite duration t of physical operations causes an idling time on those qubits that are not targeted by these operations.The idling error rate for a qubit with coherence time T 2 that is prone to pure Markovian dephasing during an idling time t is The rate p idle is linearly proportional to the idling time t if t/T 2 1. Denoting the logical failure rates of the two protocols p MF L and p SM L respectively, MFEC is advantageous when the ratio of the failure rates p MF L /p SM L ≤ 1.We estimate in App.D that the MFEC protocol is advantageous when the ratio of measurement to operation time fulfills the inequality Here, c (c) is the number of operations (idling locations) in the MFEC circuit and c is the number of idling locations during measurements in the conventional EC protocol.
As an example of a measurement-based protocol, we choose a state-of-the-art flag-qubit-based EC protocol [56], described in App.E. We pick a set of noise parameters which satisfies Eq. ( 3) with a large margin, given the constants for the flag EC circuits in Eqs.(3.44 ± 0.25)% when compiled into CNOT gates while flag EC fails for p FL L = (3.96± 0.26)% of the runs.The numerical data in Fig. 5 is obtained by sampling logical failure rates of both schemes in Monte Carlo simulation until the uncertainty intervals of the two estimators allow one to distinguish which of the two schemes is advantageous.While gate error rates of p = 5 × 10 −4 are experimentally demanding, we stress that our scheme offers the possibility to perform FT QEC in physical systems that currently cannot support the measurement duration necessary for conventional QEC schemes.

III. DETERMINISTIC FT LOGICAL STATE PREPARATION
Our MFEC scheme needs logical auxiliary qubits whose encoding must be FT in order to render the full scheme FT.In this section we describe how to faulttolerantly initialize the logical auxiliary qubit (and also the logical data qubit) without measurements.This way, our FTEC scheme can be performed in a fully measurement-free setting.Let us remark nevertheless that the measurement-based encoding protocol from Ref. [72] has been realized recently in ion-trap platforms [11,13,15].
In Ref. [57] some of us suggest an extension of the prescription for logical qubit initialization in Ref. [72] by making use of the flag qubit information instead of discarding the state.The circuit for measurement-free FT initialization to |0 L is shown in Fig. 6.By mapping the two eigenvalues of both the logical operator Z 3 Z 5 Z 6 (red block, "flag") and the complementary stabilizer Z 1 Z 2 Z 4 Z 7 (orange block, "stabilizer") to two auxiliary qubits, all dangerous weight-2 errors at the end of the circuit can be transformed into correctable errors.
In fact, there are only two dangerous errors, namely X 1 X 3 and X 4 X 5 (X 6 X 7 is stabilizer-equivalent to X 4 X 5 via application of K X 1 ), which flip the first auxiliary qubit from |0 to |1 since their support has odd overlap with Z 3 Z 5 Z 6 .Of course, X 1 X 3 and X 4 X 5 also have odd overlap with the qubits that take part in the subsequent stabilizer mapping step so the second auxiliary qubit is also flipped from |0 to |1 .The dangerous errors will lead to both auxiliary qubits being in the |1 state.Correctable weight-1 errors only flip one of the two from |0 to |1 .No single fault during the mapping of either Z-operator can result in the auxiliary qubits being in the state |11 .The operator X 7 is applied coherently via the Toffoli gate if both the flag qubit and the extra stabilizer qubit are in the |1 state (green block, "feedback").This way, any dangerous weight-2 error will be transformed into a correctable weight-1 error by multiplication with X 7 .Treatment of the X 1 X 3 error is sketched as an example in Fig. 6.
The auxiliary qubit state before applying the Toffoli gate can only be different from |00 if a fault has hap-FIG.6. Circuit to fault-tolerantly initialize the logical zero state of the Steane code without measurements.The first eight CNOT gates prepare the state non-fault-tolerantly.The subsequent three CNOT gates map the logical operator Z3Z5Z6 to a flag qubit that heralds successful preparation (red dotted circles on code graph).The last four CNOT gates map the complementary stabilizer Z1Z2Z4Z7 (orange dashed circles on code graph) to a second auxiliary qubit.Only if both measurements yield the −1-eigenvalue, the correction X7 is applied via the Toffoli gate (large green circle on code graph).In the end, both auxiliary qubits are reset (R).The dangerous fault X1 after the fourth CNOT gate (red star) propagates to both auxiliary qubits and triggers the Toffoli feedback (green box).The resulting operator X1X3X7 is stabilizer-equivalent to the correctable error X5 via application of 7. Decomposition of the Toffoli gate followed by reset of the control qubits into Hadamard gates H, the standard T, T † and CNOT gates as well as reset R.
pened at some circuit location before.An additional fault during the Toffoli gate would render the total fault configuration to be of order p 2 .If instead the circuit up to the Toffoli gate has been fault-free and the t = 1 fault now occurs within the Toffoli gate with probability p, it can at most propagate to a correctable error since the Toffoli is only connected to a single data qubit.
The Toffoli gate can be decomposed into a sequence of single-and two-qubit gates. 2 Since the auxiliary qubit state is discarded at the end of the circuit anyways, we can modify the well-known decomposition into six CNOT gates from Ref. [59]. Figure 7 shows the decomposition of the Toffoli gate followed by reset into only four CNOT gates.
In summary, since the state preparation scheme can be performed without qubit measurements, it qualifies to prepare logical auxiliary qubits and thereby completes our measurement-free FT QEC scheme.

IV. PRACTICAL IMPLEMENTATION
The suggested measurement-free fault-tolerant quantum error correction protocol can be implemented using various sets of basis gates that are native to different quantum computing platforms.In the following, we provide compilations of our 17-qubit scheme (Fig. 2) into CNOT gates, native multi-qubit-controlled gates as well as multi-qubit Mølmer-Sørensen gates.The latter are widely-used entangling gates in trapped-ion systems [74].
If native multi-qubit gates are practically available and if their physical error rates are lower than the expected overall error of their decompositions, they are preferential to implement the feedback operation (green boxes in Fig. 2) over a gate decomposition into single-and twoqubit gates in order to minimize circuit depth.For the syndrome mapping step (orange boxes in Fig. 2), multiqubit gates can still be used to decrease the gate count.It is crucial that the transversal CNOT gates used for fault propagation (yellow boxes in Fig. 2) cannot be replaced by multi-qubit gates.These would destroy the FT property of the scheme under a general error channel (see 2 We note that the reduced Toffoli gate decompositions given in Refs.[71,73] are not feasible for use in our scheme.There, the Toffoli operation is performed up to a relative phase between certain computational basis states, which would lead to erroneous phase flips when applied to a superposition state such as |0 L . Eq. (C1)) since single faults could result in higher-weight errors that are uncorrectable in the Steane code.
To be truly fault-tolerant, every qubit operation used in an actual implementation acting on a respective qubit state ρ must be assumed to be prone to noise.Here we employ the standard depolarizing noise model (see App. C for details) with different noise strengths than in Sec.II C: For the decomposition into two-qubit gates, we show simulations for a single-parameter depolarizing noise model with noise strength p on operations.On idling locations, we choose a corresponding noise strength p/100, which is the order of magnitude reached for twoqubit entangling gates in state-of-the-art ion trap systems [75].This model has been assumed before for simulation of QEC blocks [54,76].For the decompositions into multi-qubit gates, we use a multi-parameter noise model with different noise strengths p = (p 1 , p 2 , ...) for the respective multi-qubit depolarizing channel (see Eq. (C1)) on operations.The parameters are based on values that either can be achieved experimentally in quantum processors already [15,75] or are based on theory proposals [77][78][79][80].Since dephasing is the dominant source of noise on idling qubits in atomic architectures, we make use of the dephasing channel (see Eq. (C2)) with noise strengths assumed to be p/100 for simplicity 3 on the respective idling locations for the multi-parameter noise model.To assess the break-even point where p L = p 2 , we scale all physical error rates uniformly with a scaling parameter λ like (p 1 , p 2 , ...) → λ • (p 1 , p 2 , ...).
Numerical statevector simulations of these noisy circuits are performed with a modified version of the python package PECOS [83,84].

A. Decomposition in two-qubit gates
A large extent of the scheme is already expressed in terms of CNOT gates.The only components left to decompose are the multi-qubit-controlled feedback gates C 3 NOT and C 3 Z.The authors of Ref. [71] state that 13 two-qubit gates are necessary to exactly decompose the full gate.However, since the state of the control qubits 3 The order of magnitude is estimated from gate and coherence times of alkali-atom-platforms.With p 2 = 5 × 10 −3 , t 2 ≈ 250 ns [81] and T * 2 ≈ 4 ms (T 2 ≈ 1 s when spin echo techniques are applied) [20,82] we find a ratio of p 2 /p idle,2 ≈ 160 (4 × 10 4 ).For ion traps, multi-qubit gate parameters are given in Ref. [77].For example for the five-qubit MS gate, the noise strength p 5 = 5 × 10 −2 and duration of t 5 = 60 µs would correspond to a factor of p 5 /p idle,5 ≈ 166 with a coherence time T 2 = 100 ms.In other ion trap platforms [31,75] the ratio can be somewhat higher, for example for the two-qubit gate with p 2 = 2 × 10 −3 that takes time t 2 = 25 µs and corresponds to a factor of p 2 /p idle,2 ≈ 320 with a coherence time is reset after the gate anyways, decomposition is possible with fewer CNOT gates.Figure 8 shows the circuit equivalence of C 3 NOT and a sequence of eight CNOT gates and standard single-qubit rotations when the state of the three control qubits after the gate is irrelevant.Alternating rotations of angle ±π/8 cancel each other exactly if the control qubit state is different from |111 .Only if all CNOT gates are activated, the intermediate X-flips make the eight Z-rotations align in order to realize a full X(π)-rotation in combination with the outermost Hadamard gates on the target qubit.In Fig. 9 we compare the logical failure rate of the MFEC scheme with CNOT gates to the conventional flag EC from Sec. II C. Quadratic scaling behavior p L ∼ p 2 as p → 0 for both logical input states |0 L and |+ L is clearly visible in Fig. 9.This is expected for the two FT schemes since there exist no single fault events that occur with probability p and contribute to the logical failure rate p L .Our MFEC scheme achieves logical failure rates p L approximately one order of magnitude larger than the flag scheme for a given physical error rate p.
To narrow the gap between the two schemes and achieve lower logical failure rates with the MFEC scheme, we now look into possible improvements using multiqubit gates.

B. Use of multi-qubit gates
Depending on the physical architecture under consideration, specific multi-qubit gates might be available for practical operation of the scheme.In neutralatom platforms, the Rydberg blockade can be utilized to perform native multi-qubit gates.CCZ gates that require only global laser pulses have already been realized in experiments [81,85].Moreover, there are multiple theoretical proposals to implement, e.g., C n NOT gates [80,81,86,87], CNOT n gates [87,88] or C n NOT m gates [89], up to single-qubit rotations.In ion traps the iToffoli gate with varying number of control qubits can be implemented directly [79,90].Additionally, one can realize multi-ion MS gates in these systems [42,74].Also in superconducting architectures there are proposals and demonstrated implementations of native iToffoli [91,92] and CCPHASE gates [93].
In the following we provide decompositions and numerical simulations of the MFEC scheme using different sets of multi-qubit gates where possible.Logical failure rates of these compilations are compared via numerical simulation to the scheme that uses only CNOT gates.
Native multi-qubit-controlled feedback in neutral-atom platforms.We now describe the usage of native C 3 NOT gates for feedback operations (green boxes in Fig. 2).With the large fidelities and fast gate times of such gates (see Table I and Refs.[77][78][79][80]) an improvement of logical failure rate can be expected over a decomposition into two-qubit gates, also due to the reduction of idling locations.From inspection of Fig. 8 we notice that due to the reset operations only the target qubit can cause erroneous output of the multi-qubit-controlled feedback gate.In this decomposed version, eight two-qubit gate locations and ten single-qubit gate locations can cause an error in first order in p.We thus estimate that using a native multi-qubit-controlled feedback gate to be advantageous over the decomposition as long as p 4 < 8p 2 + 10p 1 at least, which is fulfilled for the parameters in Table I.
Coherent syndrome mapping and quantum  I. Depending on the implementation, logical failure rates can vary to up to one order of magnitude.
feedback in ion traps.The 17-qubit scheme for the Steane code from Fig. 2 can be embedded into a trapped ion quantum processor, as sketched in Fig. 3b, hosting a static one-dimensional ion crystal as in Ref. [25].In these systems, the native entangling gate can be implemented by a laser-driven X-type MS gate described by the unitary targeting q ions simultaneously [74,94].Such multi-qubit MS gates can be used for the syndrome mapping (orange boxes in Fig. 2) and feedback steps [41,95].Previously it has been found by exhaustive count of gate combinations in Ref. [96] that the Toffoli gate is equivalent to a sequence of local rotations and MS 3 gates (reproduced in Fig. 16 of App.F), which we do not improve further for use in our QEC scheme.An application of MS 5 gates for mapping the expectation value of a weight-4 stabilizer to a single auxiliary qubit has been given in Refs.[77,95] (see App. F for an example in Fig. 17).Six MS 5 gates are needed to map the syndrome to the physical auxiliary qubits.Recall that high-weight Pauli faults that are generated by the depolarizing noise channel of the MS 5 gate do not break fault-tolerance since they only act on the logical auxiliary qubit, which is reset after syndrome mapping.
Figure 10 shows logical failure rates for all three previously described implementations for MFEC for both logical Steane code input states |0 L and |+ L .Notably, all implementations are capable of achieving logical failure rates p L < p 2 lower than the two-qubit error rate with improvements of the scaling factor λ of approximately one order of magnitude.For low physical error rates, where the six lines in Fig. 10 are (almost) parallel, native multi-qubit-controlled feedback operations yield approximately a factor five of improvement over the CNOT compilation of the scheme.Multi-ion MS gates perform approximately a factor of two worse than the CNOT version in this regime 4 .

C. Implementation with neutral atoms
As mentioned above, measurements in neutral-atom platforms are slow as compared to gates and it is challenging to perform measurements without atom loss and with real-time feedback.While multi-qubit gates can be performed within roughly 100 -500 ns [81,85,98,99], recently demonstrated mid-circuit measurements in free space take 3.5 -25 ms [32][33][34][35].Such values correspond to ratios t meas /t ops between 7 × 10 3 and 2.5 × 10 5 .
With a coherence time of T * 2 = 4 ms, we estimate the logical failure rate of MFEC using native multi-qubitcontrolled feedback gates via numerical simulation to be p MF L = (5.9±0.3)%.With measurement times of approximately t meas ∈ {500 µs, 1 ms}, flag EC achieves respective logical failure rates of p FL L ∈ {(4.9±0.2)%,(11.8±0.4)%}.Assuming an anticipated improvement of future operation error rates p 1 , p 2 , p 3 , p 4 and p i by a factor of 2, the 4 The syndrome mapping step in this variant is expected to be more noisy since 6p 5 > 12p 2 as compared to the CNOT version with the parameters from Table I.Also note that the decomposition into MS gates requires additional single-qubit rotations compared to the CNOT version, which we did not optimize for these simulations.
logical failure rate of MFEC drops to p MF L = (1.7±0.1)%,i.e. by about a factor of 4, in agreement with the expectations for an FT protocol.
Using the substantially longer coherence time T 2 = 1 s, which can be achieved by involving spin-echo techniques, the failure rate of MFEC is reduced only slightly to p MF L = (5.6 ± 0.1)%.This can be understood because the performance of the MFEC protocol is in this parameter regime not limited by its overall duration, but operational error rates.In contrast, the performance of the flag EC protocol improves more strongly, with the scheme benefiting more from an extended coherence time, resulting in a logical failure rate of p FL L = (0.66 ± 0.04)% for a measurement time t meas = 1 ms.Improving the operation error rates by a factor of 2 yields a predicted MFEC logical failure rate of p MF L = (1.7±0.1)%.The simulated 5 failure rates are summarized in Table II.
Our proposed scheme might thus open a competitive pathway for this platform to achieve beneficial FT QEC before fast in-sequence measurements and in-sequence logic will become widely available.Although leakage out of the computational subspace is a dominant error source in neutral-atom platforms, such errors can be handled either by converting them into Pauli Z-errors [21] or erasures [22].To execute the quantum circuits presented in this work, a certain connectivity between qubits is required.In a static array of atoms with nearest-neighbour or even next-to-nearest-neighbour interactions this would 5 For the simulations, we choose realistic operation error rates  2) [20,81].For measurement times tmeas ∈ {500 µs, 1 ms} we employ idling error rates p idle,m ∈ {5.9 × 10 −2 , 11.8 × 10 −2 } (p idle,m ∈ {2.5 × 10 −4 , 5 × 10 −4 }) that follow from the values of T * 2 (T 2 ) stated above.
require many SWAP gates.In neutral-atom quantum processors, however, individual atoms can be dynamically rearranged during a computation, which yields a very good effective qubit connectivity [20,100,101] but can increase effective gate times.Moreover, the multiqubit gates required for our scheme are natively available in this platform [81].
In Fig. 11 we propose a layout of atoms in a tweezer array, together with shuttling moves, to realize the measurement-free FT QEC scheme in an experiment.We assume a near-term neutral-atom platform with a global Rydberg laser illuminating all atoms in the tweezer array.This allows to perform two-qubit gates or multi-qubit gates on sets of atoms that are located within the blockade radius of each other.If those sets of atoms are placed sufficiently far away from each other, such gates can be performed in parallel [20,81].Furthermore, we assume that atoms can be locally addressed to perform individual single-qubit gates.If also single-qubit gates can only be performed globally, additional shuttling moves of subsets of atoms into dedicated single-qubit gate operation zones are necessary.The left-hand side of Fig. 11 shows a circuit that realizes the measurement-free FT correction cycle for X-errors.On the right-hand side we first depict the initial layout of 35 atoms in the tweezer array.As described in Sec.II, the higher number of qubits avoids that qubits have to be reset during the computation and allows for a minimal circuit depth.If in-sequence qubit reset is available, it is also possible to work with 17 atoms in a tweezer array, realizing the circuit shown in Fig. 2. We sketch the application of parallel two-and multi-qubit gates as well as shuttling moves, which are performed between the application of entangling gates.The application of single-qubit gates is not shown.We choose the atom layout in a way such that the total number of shuttling operations remains small and many parallel qubit moves are possible.The scheme requires a static 2D tweezer array, generated e.g. by a spatial light modulator (SLM), and a movable tweezer array realized with a single 2D acousto-optic deflector (AOD).Parallel moves of rows and columns are possible for atoms placed in the AOD array while atoms placed in the SLM tweezers remain fixed.Between shuttling operations, atoms can be relocated from static SLM tweezers into the dynamic AOD tweezers and vice versa [102,103].Our proposed shuttling protocol thus requires 9 parallel moves of atoms, which is comparable in complexity to already demonstrated experiments [20].

V. CONCLUSIONS & OUTLOOK
In this work, we have presented a novel scheme for fault-tolerant quantum error correction without the need to measure individual physical qubits to read out the syndrome.
As we showed by numerical simulation, the measurement-free FT QEC scheme achieves logical FIG.11.Proposal for the implementation of the measurement-free FT QEC scheme with mobile neutral atoms in optical tweezers.The steps (1)-( 9) correspond to the time steps as shown on the left-hand side of this figure and in Fig. 4. Ellipses that encircle sets of atoms correspond to the parallel application of entangling gates.Arrows indicate shuttling moves after the gate executions.Single-qubit gates are not shown.
failure rates approximately one order of magnitude higher than the corresponding flag error correction protocol with single-parameter circuit-level depolarizing noise.Additionally, compilations of our scheme into different native gate sets can lead to variations and reductions in logical failure rates of up to one order of magnitude for the physical error rates we considered.This offers room for optimization to bridge the gap between the measurement-free and the conventional FT QEC schemes.We expect that a platform, which can realize an advantageous compilation, for instance using native multi-qubit-controlled gates with sufficient gate fidelities, can in this way at least partly compensate the extra infidelity introduced by the additional overhead in the measurement-free scheme compared to conventional syndrome-measurement EC.For a set of realistic parameters in a neutral atom setup, we showed via numerical simulation that the measurement-free FT QEC cycle can outperform flag-FT EC in the regime where system performance is limited by coherence time.Moreover, in neutral-atom platforms the outlined scheme may prove particularly useful due to the challenges posed by fast, low-loss and fully parallelized measurements and real-time feedback.Furthermore, neutral atoms natively feature the possibility to realize multi-qubit gates required for our scheme.Many of the required key components have been demonstrated recently in experiments, including mid-circuit shuttling of atoms and parallel application of two-qubit and multi-qubit gates [20,81].Hardware-specific noise characteristics such as biased noise or bias-preserving gates [21], could even further compensate for the overhead of the measurement-free scheme.In this sense our simulations with depolarizing noise might be overly pessimistic.
However, also an embedding of the scheme into a solidstate platform is not futile since we do not require full all-to-all qubit connectivity.Optimizing the compilation of a scheme to hardware constraints like qubit connectivity in a systematic way could also further improve the scheme.It is an open question how additional physical qubits could be used for an embedding with reduced connectivity without breaking fault tolerance, for instance by using the techniques of Refs.[104,105].
Extending our scheme to larger distance codes poses additional requirements for the construction of suitable fault-tolerant circuits on the auxiliary system.This is required to ensure that multiple faults do not cause a logical failure, which could be subject of future work, e.g.adapting concepts proposed in Refs.[54,55].Using concatenation for scale-up could provide an alternative route worth exploring.
Additionally, developing new measurement-free versions of FT logical gates or FT gadgets such as code switching or lattice surgery would further enlarge the toolbox of measurement-free FT quantum computing protocols and thereby assist in enabling error corrected universal quantum computation in future hardware platforms.code is defined by the stabilizers and its logical operators can be chosen as X L = X 1 X 6 X 7 and Z L = Z 1 Z 2 Z 3 as shown in the insets of Fig. 12.The look up table that is used in our measurement-free EC protocol to correct errors in the surface code is given in Table III.For example, the error X 4 X 6 is correctable because its Z-syndrome {−1, −1, −1, −1} is not taken up by any other weight-1 X-error.Due to the asymmetric arrangement of plaquettes, the error Z 4 Z 6 is not correctable.Its X-syndrome {+1, −1, −1, +1} is already in use to correct the weight-1 error Z 5 .This is why applying a multi-controlled-multi-target gate for the correction of X 4 X 6 would destroy fault tolerance.In our scheme, however, a multi-controlled feedback gate will only couple to a single data qubit in order to preserve fault tolerance.Weight-2 errors could still be corrected by copying the respective syndrome twice and applying two distinct weight-1 feedback operations conditioned on this same syndrome instead of applying one weight-2 feedback operation.For instance, the Z-syndrome {−1, −1, −1, −1} must be copied twice to correct X 4 and X 6 distinctly.This, however, would increase the circuit depth and gate count of the coherent feedback circuit block considerably.Instead of applying weight-2 corrections, it is sufficient to transform weight-2 errors into correctable weight-1 errors -these will be corrected for in the subsequent EC round.This is sufficient to have a fully FT EC protocol.This conversion of weight-2 into weight-1 errors can be achieved for X-and Z-errors by the recovery operations given in Table III, which are translated into the feedback structure of the circuits in Fig. 12.Note that no weight-2 recoveries need to be applied.For the error X 4 X 6 for instance, the circuit applies the recovery X 6 and leaves the correctable error X 4 on the logical data qubit.Note that, at the same time, all nine possible weight-1 errors will be corrected by the protocol, as required.Overall, this provides a compact fully FT and MF protocol, with the respective EC half-cycles for X-and Z-type correction implemented by the circuits in Fig. 12a and b, respectively.Measurement-free and FT initialization of the auxiliary logical qubit is possible using, e.g., the encoding protocol recently demonstrated in Ref. [58].
TABLE III.The 4-bit Z-syndrome (upper half) of the surface code shown in the inset of Fig. 12a allows one to correct not only all 9 single-qubit X-errors but also some additional weight-2 X-errors.Note that, for instance, applying X8 corrects both errors X8 and X9 since K X 1 = X8X9 is a stabilizer.The third column contains the recovery operations that are applied by the circuit in Fig. 12 and the last column shows that the result RE is always an error of at most weight-1.The X-syndromes and corresponding Z-type operations are given in the lower half of the table and the X-stabilizers are shown in the inset of Fig. 12b.

Appendix B: Decoding variant
The syndrome mapping step from the n physical qubits that hold the logical auxiliary qubit state to the a physical qubits that hold the syndrome information can be simplified because the logical auxiliary qubit is discarded after the syndrome mapping anyways.Instead of supplying fresh auxiliary qubits, one may replace the syndrome mapping step (orange box in Fig. 2a) with a decoding circuit.This can reduce the required number of qubits to FIG. 13.Performing an inverse encoding circuit for the |+ L state leaves the Z-syndrome (K Z 1 , K Z 2 , K Z 3 ) on qubits 4, 1 and 2 of the orange block as indicated respectively by the RGBcolored circles.The syndrome mapping step (orange box in Fig. 2a) is replaced with the decoding block and the copy and feedback steps are adjusted accordingly.In the absence of noise, each of the four other physical qubits is in the |0 state after decoding (dashed white circles).
perform the MFEC cycle to N = 2n.The decoding circuits can be constructed by inverting encoding circuits of, for instance, surface code or color code states with similar numbers of CNOT gates as the syndrome mapping [106,107].An example for the X-correction block of the Steane code, where the logical auxiliary qubit is initialized to the |+ L state, is shown in Fig. 13.Here, the physical qubits 1, 2 and 4 carry the expectation value of the Z-type stabilizer generators K Z 2 , K Z 3 and K Z 1 respectively.The expectation value is +1(−1) if the physical qubit is in the |0 (|1 ) state.
Note that, as for the syndrome mapping described in the main text, the decoding block itself does not need any fault tolerance overhead for the full MFEC scheme to be fault-tolerant.If there are not enough physical qubits after the decoding step to coherently copy the syndrome information, additional auxiliary qubits must be supplied.
The minimal circuit depth is unchanged with this modification of the orange block since the decoding in Fig. 13 needs four time steps, just as the syndrome mapping.However, one could use, for instance, a sequence of only three MS 4 gates, if practically available, to perform the decoding step [108].

Appendix C: Noise model
We consider the depolarizing channel of strength p where Λ = {I, X, Y, Z} ⊗q \{I ⊗q } and q is the number of qubits the noise channel acts on.It is the most gen-eral noise channel in the sense that the 4 q Pauli operators (and the identity operation) form the basis of the q-qubit Pauli group.Thus, any fault that can happen in a physical gate can be expressed in this Pauli basis.As a consequence, if the circuit is FT under the channel in Eq. (C1), then it is FT towards any noise channel on the q qubits.
For the single-parameter noise model in Secs.II C and IV A we use the conventional depolarizing noise model where Additionally, for the multi-parameter noise model in Secs.IV B and IV C, q-qubit gates are followed by Pauli faults drawn randomly and uniformly from {I, X, Y, Z} ⊗q \I ⊗q with respective probabilities p q .For modelling of dephasing noise on idling locations during multi-qubit gates, initializations and measurements in Secs.IV B and IV C, we use the single-qubit channel E p idle,q (ρ) = (1 − p idle,q )ρ + p idle,q ZρZ (C2) with respective idling error rates p idle,q during q-qubit gates and a rate p idle,i (p idle,m ) during physical qubit initialization (measurement).

Appendix D: Details of MFEC performance
In this section, we provide the analytical estimation of a parameter region for advantageous use of the MFEC scheme, given by Eq. ( 3).First, we look at the two limits were only one type of noise, either on physical operations or idling locations, is present in the system.Then we interpolate between these limits and estimate parameter regions of advantageous use of either the MFEC or the SMEC protocol.
Let us consider the limit of vanishing physical operation error rates p → 0 first so that only idling noise is present in the system.Then, MFEC is advantageous over SMEC when its QEC cycle time τ MF < τ SM is smaller than the syndrome measurement EC cycle time.For their logical failure rates this means that then p MF L /p SM L < 1.
For an FT protocol, the ratio of logical failure rates is proportional to the squared cycle time ratio if idling were the only source of failure and we operate in a regime where τ T 2 .Single faults of probability p idle ∼ τ cannot lead to failure due to the FT circuit design of the protocol.
Assuming that a single operation in the MF protocol takes time t ops , we can estimate the total cycle time as in case all operations are executed sequentially.When the SMEC protocol cycle time is dominated by the time t meas to perform a qubit measurement, i.e. we assume that measurements take much more time than gate operations, we can estimate As another limiting case, we assume no idling noise at all, i.e. the coherence time T 2 → ∞, so that the operation error rate p = 0 is the only non-vanishing physical error rate.In this case, the logical failure rates scale like for p 1 since no single fault of probability p can cause a logical failure.The two constants c 2 and c 2 are determined by the number of bad locations, i.e. fault locations that can lead to failure, for each respective protocol.Their ratio determines the (dis-)advantage of MFEC over SMEC since Now, in a realistic scenario where both idling and operations are prone to noise, the small-p behavior of the logical failure rate will be for p, p idle 1 since at least two faults in total are needed to cause logical failure for both protocols: either two faults on operations with probability p each or two faults on idling locations with probability p idle each or one operation fault with probability p and another idling fault with probability p idle can cause logical failure.The constants c, c , b and b are determined analogously to c and c by the number of bad locations of these respective fault combinations.Here we included the respective dominant source of idling noise for both protocols; idling during operations with rate p idle,op for the MF protocol and idling during measurements with rate p idle,m for the SM protocol.Again, we assume for the latter that measurements are much slower than operations.We can upper-bound Eqs.(D7) and (D8) by assuming that the constants c, c, b, c , c and b represent the total number of respective circuit locations for two operation faults, two idling faults or both one operation and one idling fault for either protocol.Then b and b can be expressed as the products cc and c c respectively.In principle, one could also determine these constants by exhaustively counting the numbers of bad locations, i.e. placing all possible combinations of two fault operators on operation and idling locations, or estimate the fraction of bad locations to total locations via Monte Carlo simulation.The ratio of logical failure rates from Eq. (D6) is then extended to read where all contributions come with their own constants c, c , c, c .We can expand Eq. (D9) around p = 0 and p idle,op = 0 so that we include all second order terms: We roughly estimate the MF advantage p MF L /p SM L ≤ 1, as given by Eq. ( 3), whenever the ratio of idling times (or error rates, provided they are sufficiently small due to t/T 2 1) is larger then the bound set by our estimation of the error rate ratios, which translates to using Eq. ( 2).Note again that we have assumed the ratios c2 /c 2 , cc/c 2 and c 2 /c 2 for the numbers of total locations to be approximately equal to the ratios using the numbers of bad locations.The boundary between regions of advantageous use of either MFEC or SMEC is estimated approximately by Eq. (D11), which is illustrated in Fig. 5 for comparison to a state-of-the-art flag EC protocol [56].The flag scheme consists of sequentially running two blocks of three parallel stabilizer measurements.In case a non-trivial measurement occurs, an additional round of non-flagged syndrome readout is performed and the correction is inferred from the flag error set and the Steane code's look up table (see App. E for details).All gate operations are executed sequentially, i.e. with only one gate per time step.Physical qubit initializations and measurements are executed in parallel in the simulation.For the MF scheme the numbers of locations are   The flag EC scheme used for comparison in Secs.II C, IV A and IV C was suggested in Ref. [56] and has been recently implemented with trapped ions [13,15].It consists of application of the two circuits shown in Figs. 14  and 15.
As a first step, all stabilizers are measured in an interleaved way with the help of six auxiliary qubits.When all six qubits are measured as +1, we know that no uncorrectable error is present on the data qubits.When any of the qubits is measured as −1 however, we cannot tell whether faults have propagated from within the measurement circuit to the data qubits or there have been faults on the input state already.The additional round of syndrome readout, performed as a second step, is needed to clarify the syndrome of the faulty state.If the syndrome is different from the previously measured one, we interpret the measurement outcome of the first block as a flag event.This means that we apply the appropriate two-qubit correction according to the flag error set if the syndrome is consistent with the possible two-qubit errors.Otherwise, or if the two measured syndromes agree, we apply the single-qubit correction according to the Steane code's look up table.This way, logical failures can only happen with probability O(p 2 ).

Appendix F: Multi-ion MS gate circuits
In the following, we list the components needed to compile the MFEC scheme in Fig. 2  for a gate acting on qubits i and/or j [109].
Toffoli gate.The Toffoli gate decomposition into three MS 3 gates and local rotations from Ref. [96] is reproduced in Fig. 16.
Syndrome mapping.The circuit that uses two MS 5 gates for mapping of a stabilizer expectation value to a single auxiliary qubit from Refs.[77,95] is reproduced in Fig. 17 for the stabilizer K Z 1 .The circuits for the other Z-type stabilizers are analogous.For the mapping of Xtype stabilizers, no Y -rotations on the data qubits must be applied.
C 3 NOT gate.The C 3 NOT gate followed by reset of the control qubits can be decomposed into four MS 4 gates as shown in Fig. 18.We found the decomposition using a parametrized circuit ansatz in pennylane [97].The parameters x are the 64 rotation angles that parametrize the four MS 4 gates and layers of arbitrary X-, Y -and Zrotations on each qubit before and after the MS 4 gates.As a cost function, we use the weighted average of the Pauli-X and -Z expectation value of the target qubit for application of the parametrized circuit unitary U ( x) to all 16 computational basis states and additional 16 states with the control qubits in the computational basis and the target qubit in the polar basis.The expectation values of the states U ( x) |1110 , U ( x) |1111 , U ( x) |111+ and U ( x) |111− are multiplied by −7/2 while all other states have weight −1/2 so that the minimal cost function value is −28.We keep optimizing the circuit parameters using the AdagradOptimizer in pennylane until the minimal value is found with an absolute tolerance of 10 −4 (see Fig. 19).The converged angles for all 64 gates in the parametrized circuit are given in Table IV.
FIG. 16.The Toffoli gate used for the quantum feedback in Fig. 6 can be compiled to multi-ion MS gates given by Eq. ( 8) and local rotations Rσ = exp −i θ 2 σ with σ ∈ {X, Y, Z} [96].The first two wires are the control qubits and the third wire is the target qubit.The decomposition is exact.The last X-and Y -rotations on the control qubits could be omitted in our case due to the subsequent reset.
FIG. 17. Circuit to read out the stabilizer K Z 1 = Z4Z5Z6Z7 using two 5-qubit MS gates with θ = ± π 2 and single qubit rotations [77,95].The stabilizer eigenvalue is mapped to the last qubit by the gate sequence.To read out the corresponding X-type stabilizer, the Y -rotations on the data qubits must be omitted.FIG.18. Compiled circuit with rounded rotation angles that implements the C3NOT gate followed by resetting the control qubits.The first three wires are the control qubits and the fourth wire is the target qubit.FIG.19.The cost function converged to the target value of −28 for the parametrized circuit in Fig. 18.

FIG. 3 .
FIG. 3. Sketched embedding of the scheme for the Steane code into (a) a neutral-atom tweezer array and (b) a static linear ion trap.For the tweezer array, we show a proposed initial configuration of the atoms.Entangling gates can by applied in parallel to atoms at close range.Between the application of entangling gates, atoms are shuttled to new locations, which we outline in more detail in Fig. 11.
FIG. 5. Utility diagram for measurement-free (MF) EC and flag EC.Regions of advantage based on numerical simulation (markers) and the estimation in Eq. (3) (filled area) are shown in terms of the parameter ratios p/p idle,op and p idle,m /p idle,op , which approximates tmeas/tops, with c2 /c 2 = 171041, cc/c 2 = 13471 and c 2 /c 2 = 1061 in accordance with Eqs.(D13)-(D16).The lines mark the estimated boundaries between regions of advantage.In the limit of vanishing operation errors, p = 0, MFEC yields an advantage over flag EC if measurements are at least 400 times slower than operations.The star marker represents the parameters given in Eqs.(4)-(6).At p/p idle,op = 1 and p idle,m /p idle,op = 1, we use absolute values of p = p idle,m = p idle,op = 10 −4 in the numerical simulations.

HFIG. 8 .FIG. 9 .
FIG.8.Decomposition of a triple-controlled-NOT gate followed by reset R of the control qubits into a sequence of Hadamard gates (H), CNOT gates and T8 = exp(−i π 16 Z) gates followed by reset R of the control qubits.

FIG. 10 .
FIG.10.Logical failure rates for the measurement-free scheme acting on both logical input states |0 L and |+ L with multi-parameter noise and a scaling parameter λ that uniformly varies all physical error rates.Compilation of the scheme into CNOT gates is compared to implementations using native multi-qubit-controlled feedback operations (NATF) and multi-ion Mølmer-Sørensen gates (MIMS) where applicable.Respective physical error rates are listed in TableI.Depending on the implementation, logical failure rates can vary to up to one order of magnitude.

FIG. 12 .
FIG. 12. Measurement-free FT QEC cycle for the distance-3 surface code based on the look up table in Table III.(a) Xcorrection block with the correctable weight-2 error X4X6 (red stars), which is transformed to X4.(b) Z-correction block.Note that 7 (3) out of 10 feedback operations in each block are conditional 3-qubit-controlled (4-qubit-controlled) multi-qubit gates.
1. a single-qubit gate is followed by a Pauli fault drawn uniformly and independently from {X, Y, Z} with probability p/3, 2. a two-qubit gate is followed by a two-Pauli fault drawn uniformly and independently from {I, X, Y, Z} ⊗2 \I ⊗ I with probability p/15, 3. qubit initialization is flipped (|0 → |1 ) with probability 2p/3, 4. qubit measurements yield a flipped result (±1 → ∓1) with probability 2p/3 and 5. idling locations are followed by a Pauli fault drawn uniformly and independently from {X, Y, Z} with probability p/100.

FIG. 14 .
FIG.14.Parallel measurement of three stabilizers in two sequential steps realizes the flag fault-tolerant circuit for error detection[56].Due to the interleaved scheduling of CNOT gates, all six auxiliary qubits act as measurement and flag qubits at the same time.

FIG. 15 .
FIG.15.Non-flagged circuit to readout all six stabilizers sequentially.Combined with the flag information from the circuit in Fig.14, this circuit is used for FT syndrome readout.
Appendix E: Circuits for flag EC into multi-ion MS gates, as discussed in Sec.IV B. CNOT gate.For the decompositions of CNOT gates into MS 2 gates and local rotations R σ = exp −i θ 2 σ with σ ∈ {X, Y, Z} we use the identity C i NOT j