Fermion-Parity-Based Computation and Its Majorana-Zero-Mode Implementation

Majorana zero modes (MZMs) promise a platform for topologically protected fermionic quantum computation. However, creating multiple MZMs and generating (directly or via measurements) the requisite transformations (e.g., braids) pose significant challenges. We introduce fermion-parity-based computation (FPBC): a measurement-based scheme, modeled on Pauli-based computation, that uses efficient classical processing to virtually increase the number of available MZMs and which, given magic state inputs, operates without transformations. FPBC requires all MZM parities to be measurable, but this conflicts with constraints in proposed MZM hardware. We thus introduce a design in which all parities are directly measurable and which is hence well suited for FPBC. While developing FPBC, we identify the “logical braid group” as the fermionic analog of the Clifford group.

Figure 1

An arbitrary fermionic circuit $C$ on register ${\mathcal{R}}_n$, to be simulated by FPBC. The $T_2$ gates are enacted via magic state gadgets (dashed boxes), with magic states encoded in register ${\mathcal{R}}_t$. The gadgets involve a two-register fermion parity measurement $M_j^0$ and a measurement-dependent logical braid $R_j$. $C$ involves $t$ uses of the gadget, interspersed with logical braids $B_i$, and ends with the measurement of all $s_j^{(c)}$. Dummy measurements of all $s_j^{(c)}$ are appended to the start of $C$.

Figure 2

Section of FPBC hardware. Left: top and bottom black dashed regions are superconducting plates—the bus and phase ground, respectively. Thick black lines correspond to nanowire-hosting superconducting islands while black dots indicate trijunctions between nanowires. The design may be continued to the right and left. Right: more detailed illustration of the region indicated. Superconducting plates and islands are shown in blue. Nanowires (yellow) host Majorana bound states (labeled 1, 2, and 3) at their ends, combining to form a single Majorana zero mode at each trijunction (dashed circles). In both panels, tunable Josephson junctions are indicated with red lines.

Figure 3

The configuration for measuring any parity operator $M$ is obtained by combining five basic paths [labeled (a)–(e)] of bus-connected islands; these are the shortest clockwise paths connecting pairs of MZMs. Paths (a)–(d) have variable length while Path (e) has a fixed length. Solid (dashed) lines in all panels indicate bus-connected (ground-connected) islands. Filled (unfilled) dots are MZMs that do (do not) feature in $M$. Only “on” Josephson junctions are indicated (red lines); others are omitted for clarity. As an example, Panel (f) shows the measurement configuration for a 12-MZM parity operator. The MZMs are indexed as in the main text and basic paths connect MZMs $j$ and $j+1$ for odd $j$. When combining the basic paths, precisely those islands belonging to an odd number of paths are bus connected.