Abstract
We analyze the performance of a quantum computer architecture combining a small processor and a storage unit. By focusing on integer factorization, we show a reduction by several orders of magnitude of the number of processing qubits compared with a standard architecture using a planar grid of qubits with nearest-neighbor connectivity. This is achieved by taking advantage of a temporally and spatially multiplexed memory to store the qubit states between processing steps. Concretely, for a characteristic physical gate error rate of , a processor cycle time of 1 microsecond, factoring a 2 048-bit RSA integer is shown to be possible in 177 days with 3D gauge color codes assuming a threshold of 0.75% with a processor made with 13 436 physical qubits and a memory that can store 28 million spatial modes and 45 temporal modes with 2 hours’ storage time. By inserting additional error-correction steps, storage times of 1 second are shown to be sufficient at the cost of increasing the run-time by about 23%. Shorter run-times (and storage times) are achievable by increasing the number of qubits in the processing unit. We suggest realizing such an architecture using a microwave interface between a processor made with superconducting qubits and a multiplexed memory using the principle of photon echo in solids doped with rare-earth ions.
- Received 11 March 2021
- Revised 20 July 2021
- Accepted 3 August 2021
DOI:https://doi.org/10.1103/PhysRevLett.127.140503
© 2021 American Physical Society
Physics Subject Headings (PhySH)
synopsis
Far Fewer Qubits Required for “Quantum Memory” Quantum Computers
Published 28 September 2021
Incorporating storage units for quantum information into quantum computers may allow researchers to build such devices with several orders of magnitude fewer qubits in their processors.
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