Improved Error Thresholds for Measurement-Free Error Correction

Motivated by limitations and capabilities of neutral atom qubits, we examine whether measurement-free error correction can produce practical error thresholds. We show that this can be achieved by extracting redundant syndrome information, giving our procedure extra fault tolerance and eliminating the need for ancilla verification. The procedure is particularly favorable when multiqubit gates are available for the correction step. Simulations of the bit-flip, Bacon-Shor, and Steane codes indicate that coherent error correction can produce threshold error rates that are on the order of ${10}^{-3}$ to ${10}^{-4}$—comparable with or better than measurement-based values, and much better than previous results for other coherent error correction schemes. This indicates that coherent error correction is worthy of serious consideration for achieving protected logical qubits.

Figure 1

The full measurement-free extraction and correction circuit for the BF code. The first three gates are for syndrome extraction. The combination of $X$ gates and ${\mathrm{C}}_3\mathrm{NOT}$ gates detect properly extracted syndromes and correct errors accordingly. If a syndrome value is incorrectly extracted, the data qubits are not affected. Reset operations are performed in the final step, indicated with $R$ operations. This circuit also demonstrates the bit-flip correction procedure for the BS code, taking each $|q_i⟩$ to be a row in the BS code. Then each cnot gate is interpreted as three cnot gates, one controlled by each qubit in the row. The ${\mathrm{C}}_3\mathrm{NOT}$ gates target any single qubit in the row. A similar procedure is required for phase errors in the BS code.

Figure 2

Error correction circuit for the Steane code for bit-flip errors. The circuit for phase errors is similar.

Figure 3

Logical error rate vs gate error rate for the Bacon-Shor code, with three different choices of memory error rate. The dotted line shows $p_{\log }=p_{\mathrm{gate}}$. The difference between the curves with memory rates of 0 and ${10}^{-5}$ is minimal.

Figure 4

Logical error rate vs gate error rate for the Steane code, with three different choices of memory error rate. The dotted line shows $p_{\log }=p_{\mathrm{gate}}$. Note the near overlap between the curves with memory rates of 0 and ${10}^{-5}$.