All-Electrical Injection and Detection of a Spin-Polarized Current Using 1D Conductors

All-electrical control of spin transport in nanostructures has been the central interest and challenge of spin physics and spintronics. Here we demonstrate on-chip spin polarizing or filtering actions by driving the gate-defined one dimensional (1D) conductor, one of the simplest geometries for integrated quantum devices, away from the conventional Ohmic regime. Direct measurement of the spin polarization of the emitted current was performed when the momentum degeneracy was lifted, wherein both the 1D polarizer for spin injection and the analyzer for spin detection were demonstrated. The results showed that a configuration of gates and applied voltages can give rise to a tunable spin polarization, which has implications for the development of spintronic devices and future quantum information processing.

Figure 1

(a) Micrograph and electric circuit showing the emitter-collector configuration used in the experiment. Electrons are focused by a small perpendicular magnetic field and travel from the emitter (E), through the 2D base region (B) into the collector (C). (b) The differential conductance of the emitter at $B=0$ with application of a source-drain bias from $V_{\mathrm{sd}}=0$ to $-1.5\mathrm{mV}$ in steps of $-0.3\mathrm{mV}$. The conductance anomaly at around $G=0.25\left(2e^2/h\right)$ starts when $V_{\mathrm{sd}}=-0.9\mathrm{mV}$. Data are offset for clarity. (c) The collector voltage (focusing signal) for $V_{\mathrm{sd}}=I_{\mathrm{sd}}=0$; the focusing voltage is nearly independent of the conductance of both emitter and collector from $2e^2/h$ to $0.25\left(2e^2/h\right)$. (d) A substantial rise in the focusing signal appears when both emitter and collector were set to $G=0.25\left(2e^2/h\right)$ and the dc source-drain biases $V_{\mathrm{sd}}=-1.5\mathrm{mV}$ and $I_{\mathrm{sd}}=30\mathrm{nA}$ were applied, respectively.

Figure 2

(a) Voltage of the first focusing peak, left, and the corresponding conductance of the collector, right, as a function of gate voltage, for various values of dc source-drain bias $V_{\mathrm{sd}}$ and $I_{\mathrm{sd}}$. Enhancement of focusing peaks only occurs near the 0.25 conductance region when dc source-drain biases are applied across both the emitter and collector. (b) Normalized peak ratio and corresponding conductance as a function of gate voltage, with $I_{\mathrm{sd}}$ set to 30 nA and $V_{\mathrm{sd}}$ swept from 0 to $-1.5\mathrm{mV}$. The peak ratio rises and then saturates when both conductance and dc source-drain bias are at the appropriate values for the appearance of the $0.25\left(2e^2/h\right)$ plateau.

Figure 3

(a) The focusing peak voltage (right half) versus B field for several emitter conductance $G_e$ from 0 to $1.5\left(2e^2/h\right)$, along with its corresponding value of $G_e$ (left half) when the source-drain bias $V_{\mathrm{sd}}=-1.5\mathrm{mV}$ is applied across the emitter. The focusing voltage is offset for clarification. The focusing peak starts to split in two when the $G_e$ starts to rise from the $0.25\left(2e^2/h\right)$ plateau. (b) Voltage of the first focusing peak versus $G_e$ when $G_c$ is locked at the 0.25 plateau. Both the split peak 1, the peak marked by $\S$ in (a), and the split peak 2, the peak marked by ★ in (a), barely change with $I_{\mathrm{sd}}$ and $G_e$. Enhancement of focusing peaks only occurs when both $G_e$ and $G_c$ are at the 0.25 regime.