Physical Fault Tolerance of Nanoelectronics

The error rate in complementary transistor circuits is suppressed exponentially in electron number, arising from an intrinsic physical implementation of fault-tolerant error correction. Contrariwise, explicit assembly of gates into the most efficient known fault-tolerant architecture is characterized by a subexponential suppression of error rate with electron number, and incurs significant overhead in wiring and complexity. We conclude that it is more efficient to prevent logical errors with physical fault tolerance than to correct logical errors with fault-tolerant architecture.

Figure 1

Universal NAND gate. (a) The output charge $N_{\mathrm{out}}$ versus input charges $N_A$ and $N_B$ for a complementary transistor technology. (b) A majority vote physically implemented by competing transistor conductances $G_n$ and $G_p$ suppresses fluctuations in input charge from the output. The entropy of suppressed fluctuations leaves the system through a coupled heat bath, such as substrate phonons.

Figure 2

Fault-tolerant universal majority gate with concatenated triplicate encoding. (a) The majority gate $M$ (and inverse $M^{-1}$) truth table. (b) Majority gate with inputs and outputs in triplicate. (c) Error correction on a triplicate encoded bit $a=a_1{a}_2{a}_3$ proceeds by replicating in triplicate with $M^{-1}$, and taking majority votes to produce the corrected bit $a=a^{\prime }{}_{1}a^{\prime }{}_{2}a^{\prime }{}_3$. (d) Concatenation recursively applies the triplicate encoding.

Figure 3

Logical error-rate versus electron number. The thermal fluctuation limit ($k_{B}T=26\mathrm{meV}$) of complementary logic error rates is compared against that of architectural fault tolerance with physical majority gates limited by thermal fluctuation or atomic disorder in the ballistic limit. A concatenated triplicate code is assumed, with nonancilla electron number $N=3^L$ highlighted by $\mathbf{o}$.