Binary full adder, made of fusion gates, in a subexcitable Belousov-Zhabotinsky system

In an excitable thin-layer Belousov-Zhabotinsky (BZ) medium a localized perturbation leads to the formation of omnidirectional target or spiral waves of excitation. A subexcitable BZ medium responds to asymmetric local perturbation by producing traveling localized excitation wave-fragments, distant relatives of dissipative solitons. The size and life span of an excitation wave-fragment depend on the illumination level of the medium. Under the right conditions the wave-fragments conserve their shape and velocity vectors for extended time periods. I interpret the wave-fragments as values of Boolean variables. When two or more wave-fragments collide they annihilate or merge into a new wave-fragment. States of the logic variables, represented by the wave-fragments, are changed in the result of the collision between the wave-fragments. Thus, a logical gate is implemented. Several theoretical designs and experimental laboratory implementations of Boolean logic gates have been proposed in the past but little has been done cascading the gates into binary arithmetical circuits. I propose a unique design of a binary one-bit full adder based on a fusion gate. A fusion gate is a two-input three-output logical device which calculates the conjunction of the input variables and the conjunction of one input variable with the negation of another input variable. The gate is made of three channels: two channels cross each other at an angle, a third channel starts at the junction. The channels contain a BZ medium. When two excitation wave-fragments, traveling towards each other along input channels, collide at the junction they merge into a single wave-front traveling along the third channel. If there is just one wave-front in the input channel, the front continues its propagation undisturbed. I make a one-bit full adder by cascading two fusion gates. I show how to cascade the adder blocks into a many-bit full adder. I evaluate the feasibility of my designs by simulating the evolution of excitation in the gates and adders using the numerical integration of Oregonator equations.

Figure 1

Time-lapsed snapshots of wave-fragments propagating in simulated BZ medium in (a) near lower threshold of excitability, $\varphi =0.079$, (b) subexcitable mode, $\varphi =0.07905$, (c) non-excitable mode, $\varphi =0.0791$. The media were perturbed by rectangular north-south elongated domains of excitation, $3\times 40$ sites in state $u=1.0$. Sites of initial segment-wise perturbation are shown by arrows. Grid size is $1125\times 250$ nodes. The pictures are not snapshots of many wave fronts generated at the initial stimulation point. These are time-lapsed snapshots of two waves (one propagating right, another left) recorded every 150th step of numerical integration.

Figure 2

Time-lapsed overlays of the fusion of two excitation wave-fragments. One fragment is traveling from north-west to south-east, another fragment from south-west to north-east. The wave-fragments collide and fuse into a new localized excitation traveling east.

Figure 3

Fusion gate. (a) Scheme: inputs are $x$ and $y$, outputs are $xy$, $\overline{x}y$, $x\overline{y}$. (a–d) Time-lapsed overlays of excitation waves. (b) Excitable mode, $x=1$, $y=0$. (c) Subexcitable mode, $x=1$, $y=0$. (d) Excitable mode, $x=1$, $y=1$. (e) Subexcitable mode, $x=1$, $y=1$.

Figure 4

Snapshots of fusion gate for inputs $x=1$ and $y=0$. Channels are always in excitable mode, $\varphi =0.05$. (a–f) Junction is in excitable mode [(a) $t=0.475$, (b) $t=6.91$, (c) $t=8.76$, (d) $t=9.955$, (e) $t=11.21$, (f) $t=13.785$]. (g–l) Junction is in subexcitable mode, $\varphi =0.0766$ [(g) $t=0.37$, (h) $t=7.14$, (i) $t=8.785$, (j) $t=10.135$, (k) $t=11.31$, (l) $t=13.605$]. The subexcitable domain is shown in light-gray in snapshot (g). Excitable heads of the wave-fragments are shown in red. Refractory tail in blue.

Figure 5

Snapshots of fusion gate for inputs $x=1$ and $y=1$. The system is in subexcitable mode. Time is (a) $t=0.475$, (b) $t=0.475$, (c) $t=0.475$, (d) $t=0.475$, (e) $t=0.475$. Excitable heads of the wave-fragments are shown in red. Refractory tail in blue.

Figure 6

A scheme of a one-bit half-adder: input channels are $a$ and $b$, output channels are $g$ and $h$, internal channels $d$, $e$, $f$, and junctions are $c$, $i$, and $j$. Input variables $x$ and $y$ are fed into channels $a$ and $b$, results $x\oplus y$ and $xy$ are read from channels $g$ and $h$.

Figure 7

Time lapsed overlays of excitation waves propagating through junctions $i$ (a,b) and $j$ (c,d). (a,b) Wave-fragment approaches junction $i$ via channel $f$ (Fig. 6). (c,d) Wave-fragment approaches junction $j$ via channel $d$ (Fig. 6). (a,c) The system is in excitable mode. (b,d) The system is in subexcitable mode.

Figure 8

Time lapsed overlays of excitation waves propagation in the one-bit half-adder (Fig. 6) for inputs (a) $x=1$, $y=0$, (b) $x=1$, $y=0$, (c) $x=1$, $y=1$. Sites of initial segment-wise perturbation are visible as discs. Grid size is $500\times 790$ nodes. The pictures are not snapshots of many wave fronts generated at the initial stimulation point. These are time lapsed snapshots of a single wave (a,b) or two waves merging into a single wave (c) recorded every 150th step of numerical integration.

Figure 9

A scheme of a one-bit full-adder: input channels are $a$, $b$, and $c$, output channels are $t$ and $u$, internal channels $e$, $f$, $g$, $h$, $k$, $l$, $n$, $o$, $p$, and junctions are $d$, $i$, $j$, $m$, $r$, $s$. Input variables $x$ and $y$ are fed in channels $b$ and $c$, Carry in is fed in channel $a$, results $x\oplus y\oplus z$ and $xy+z(x\oplus y)$ are read from channels $t$ and $u$.

Figure 10

Time lapsed overlays of excitation waves propagation in the one-bit full adder (Fig. 9) for inputs (a) $x=0$, $y=0$, $z=1$; (b) $x=1$, $y=0$, $z=1$; (c) $x=1$, $y=1$, $z=1$.

Figure 11

Scheme of four-bit full adder. Input bit-strings are $(x_0,x_1,x_2,x_3)$ and $(y_0,y_1,y_2,y_3)$ and their sum bit-string is $(s_0,s_1,s_2,s_3)$.

Figure 12

Architectures of three types of one-bit half-adders implemented in a BZ system. (a) Collision based design [30, 44]. (b) Coincidence detectors and chemical diodes based design [33] and (c) wave-fragments fusion based design.