Valleytronics in merging Dirac cones: All-electric-controlled valley filter, valve, and universal reversible logic gate

Despite much anticipation of valleytronics as a candidate to replace the aging complementary metal-oxide-semiconductor (CMOS) based information processing, its progress is severely hindered by the lack of practical ways to manipulate valley polarization all electrically in an electrostatic setting. Here, we propose a class of all-electric-controlled valley filter, valve, and logic gate based on the valley-contrasting transport in a merging Dirac cones system. The central mechanism of these devices lies on the pseudospin-assisted quantum tunneling which effectively quenches the transport of one valley when its pseudospin configuration mismatches that of a gate-controlled scattering region. The valley polarization can be abruptly switched into different states and remains stable over semi-infinite gate-voltage windows. Colossal tunneling valley-pseudomagnetoresistance ratio of over $10000$% can be achieved in a valley-valve setup. We further propose a valleytronic-based logic gate capable of covering all 16 types of two-input Boolean logics. Remarkably, the valley degree of freedom can be harnessed to resurrect logical reversibility in two-input universal Boolean gate. The ($2+1$) polarization states (two distinct valleys plus a null polarization) reestablish one-to-one input-to-output mapping, a crucial requirement for logical reversibility, and significantly reduce the complexity of reversible circuits. Our results suggest that the synergy of valleytronics and digital logics may provide new paradigms for valleytronic-based information processing and reversible computing.

Figure 1

Concepts of all-electric-controlled valley filter. (a) Band diagram of pseudospin-assisted valley-contrasting quantum tunneling structure in a two-dimensional merging Dirac cone system. The matching and mismatching of pseudospin configuration between the incident and the scattering regions allow the valley polarization of the transmitted current to be all-electrically tuned. The isoenergy contours are shown alongside with the pseudospin vectors of forward (towards-right) propagating states. Backward (towards-left) propagating states are grayed out. (b) Schematic drawing of a valley filter based on a transistor setup.

Figure 2

Reversibility and Boolean loop representations of logic gates. The four vertices of the Boolean loop represents various $(A,B)$ input configuration. Filled (emptied) node denotes “1” (“0”) output. Letter “R” emphasizes logical-reversibility. (a) Traditional irreversible NAND. (b) Reversible CNOT. (c) Reversible NAND based on Toffoli gate by holding $C=1$. (d) Valleytronic-based reversible NAND.

Figure 3

Band topology, pseudospin configuration, and valley-contrasting transport in merging Dirac cone system. (a) Topological transition of the band structure for $\mathrm{\Delta }>0$, $\mathrm{\Delta }=0$, and $\mathrm{\Delta }<0$. (b) Pseudospin texture for ${\varepsilon }_{\mathbf{k}}>0$ and for (c) ${\varepsilon }_{\mathbf{k}}>0$. Forward and backward propagation is denoted by solid and dashed contour lines, respectively. Blue and red colors denote quasiparticle states with $S_x<0$ and $S_x>0$, respectively. For (b) and (c), $\mathrm{\Delta }=-1$ is used. The innermost, intermediate, and outermost contour lines represent ${\varepsilon }_{\mathbf{k}}=(0.5,1,1.6)$ and ${\varepsilon }_{\mathbf{k}}=(-0.5,-1,-1.6)$, respectively, in (b) and (c). (d) Diagram of $\langle {\psi }_{{\mathbf{k}}^{\prime },s^{\prime }}|{\psi }_{\mathbf{k},s^{\prime }}\rangle$ for $s=+1$ (left and right bars correspond to ${\mathcal{D}}^{\prime }=\pm 1$). Empty region denotes $\langle {\psi }_{{\mathbf{k}}^{\prime },s^{\prime }}|{\psi }_{\mathbf{k},s^{\prime }}\rangle =0$. Filled and horizontally striped regions denote $\langle {\psi }_{{\mathbf{k}}^{\prime },s^{\prime }}|{\psi }_{\mathbf{k},s^{\prime }}\rangle =1$ with ${\mathcal{D}}^{\prime }=\pm 1$, respectively.

Figure 4

Operation of valley filter. (a) Band diagram of the valley filter. $\mathrm{\Delta }$ is constant throughout regimes I, II, and III. The band alignment of regime II is gate tunable via $U(0<x<d)$. Transmission probabilities $T_{+}^{(+)}$ for (b) potential barrier and for (d) potential well. (c), (e) Same as (b) and (d) for $T_{-}^{(-)}$. Valley-polarized conductance in (f) $D+$ and (g) $D-$ channels. Blue, green, and red curves correspond to ${\varepsilon }_F/\left|\mathrm{\Delta }\right|=(0.1,0.2,0.5)$, respectively. (h) Valley polarization efficiency $\eta$. $\mathrm{\Delta }=-0.1$ and $d=75$ are used.

Figure 5

Operation of valley valve and colossal valley-pseudomagnetoresistance effect. (a) Schematic drawing of valley valve. (b) Parallel and antiparallel configurations and their respective quadrant in the $V_{G1}\text{−}{V}_{G2}$ space. (c) Valley-dependent conductance $G_{\pm }$ and the corresponding $\eta$. (d), (e) Same as (c) but operated in $D+$ and $D-$ modes, respectively, via $V_s=-0.2$ and $0.2$. (f) VPMR ratio of Q1$\leftrightarrows \mathrm{Q}2$ (denoted by red squares) and Q3$\leftrightarrows \mathrm{Q}2$ (denoted by blue circles) is shown. The VPMR ratios of Q1$\leftrightarrows \mathrm{Q}4$ and Q3$\leftrightarrows \mathrm{Q}4$ are approximately identical to this plot and hence are not shown. The following parameters are used: $\mathrm{\Delta }=-0.1$, ${\varepsilon }_F/\left|\mathrm{\Delta }\right|=0.1$, the barrier width corresponding to $V_{G1,2,s}$ is set to $d_{\text{gate}}=75$ and are separated by $d_{\text{inter}}=20$.

Figure 6

Valley-transport phase diagrams (VPD) and universal reversible valleytronic logic gates. (a) VPD of the valley filter. (b) VPD for $D+$ mode and (c) $D-$ mode. One-input NOT operation is indicated by a single Boolean line in (a). The larger and the smaller loops in (a) represent Class-2A and Class-3 operations, respectively. In (b) and (c), the larger and smaller loops represent Class-1 and Class-2B operations. Physical implementation of (d) NOT, (e) reversible NAND, and (f) reversible OR gates.

Figure 7

Examples of valleytronic-based reversible Boolean circuit. (a) General scheme of a valleytronic-based reversible circuit. Three inputs (A, B, C) are operated by two gates to yield a final current output $X_2$. The input states can be unambiguously recovered via the two valley polarizations $V_1$ and $V_2$. (b) Reversible half-adder and (c) reversible full-adder with their truth table. Ambiguous operations are emphasized by dashed boxes. In these devices, the logical reversibility is established via the valley colors $V$.

Figure 8

Energy dispersion of merging Dirac cone system at $k_y=0$. The $(\lambda ,\eta )$ index of various branches is marked. The arrows denote the direction of the group velocity $v_x^{\left(\lambda \eta \right)}$. Electronlike ($v_x^{\left(\lambda \eta \right)}$ parallel with $k_x$) and holelike ($v_x^{\left(\lambda \eta \right)}$ antiparallel with $k_x$) quasiparticles are denoted by green and yellow circles, respectively.

Figure 9

Pseudospin texture of a merging Dirac cone system. (a), (b) Shows, respectively, the $x$-component pseudospin and $y$-component pseudospin textures of a merging Dirac cone system for ${\varepsilon }_{\mathbf{k}}<0$. (c), (d) Same as (a) and (b) but for ${\varepsilon }_{\mathbf{k}}>0$.

Figure 10

Intervalley transmission probabilities $T_{\mp }^{(\pm )}$, plotted with (a) $V_g=0.2$ and (b) $V_g=-0.2$ ($d=75$, $\mathrm{\Delta }=0.1$). Note that $T_{\mp }^{(\pm )}=T_{\pm }^{(\mp )}$.

Figure 11

Tunneling band diagram of valley valve device.

Figure 12

Conductance-voltage characteristic of NOT gate with a fixed $V_{G2}=0.2$. Insets show the Boolean line of NOT operation in the VPD with $V_s=0$, and the gate configurations.