Tuning electronic properties of ${\mathrm{FeSe}}_{0.5}{\mathrm{Te}}_{0.5}$ thin flakes using a solid ion conductor field-effect transistor

Using a field-effect transistor (FET) configuration with solid Li-ion conductor (SIC) as gate dielectric, we have successfully tuned carrier density in ${\mathrm{FeSe}}_{0.5}{\mathrm{Te}}_{0.5}$ thin flakes, and the electronic phase diagram has been mapped out. It is found that electron doping controlled by SIC-FET leads to a suppression of the superconducting phase, and eventually gives rise to an insulating state in ${\mathrm{FeSe}}_{0.5}{\mathrm{Te}}_{0.5}$. During the gating process, the (001) peak in x-ray diffraction patterns stays at the same position and no new diffraction peak emerges, indicating no evident ${\mathrm{Li}}^{+}$ ions intercalation into the ${\mathrm{FeSe}}_{0.5}{\mathrm{Te}}_{0.5}$. It indicates that a systematic change of electronic properties in ${\mathrm{FeSe}}_{0.5}{\mathrm{Te}}_{0.5}$ arises from the electrostatic doping induced by the accumulation of ${\mathrm{Li}}^{+}$ ions at the interface between ${\mathrm{FeSe}}_{0.5}{\mathrm{Te}}_{0.5}$ and solid ion conductor in the devices. It is striking that these findings are drastically different from the observation in FeSe thin flakes using the same SIC-FET, in which $T_c$ is enhanced from 8 K to larger than 40 K, then the system goes into an insulating phase accompanied by structural transitions.

Figure 1

(a) Temperature-dependent resistivity of as-grown and ${\mathrm{O}}_2$-annealed ${\mathrm{FeSe}}_{0.5}{\mathrm{Te}}_{0.5}$ bulk single crystals. The insert shows a typical temperature-dependent resistivity of ${\mathrm{FeSe}}_{0.5}{\mathrm{Te}}_{0.5}$ thin flake before and after gating. (b) Temperature-dependent Hall coefficient $R_H$ of as-grown and ${\mathrm{O}}_2$-annealed ${\mathrm{FeSe}}_{0.5}{\mathrm{Te}}_{0.5}$ thin flakes. (c) A schematic plot of the SIC-FET device with the solid ion conductor as the gate dielectric. The solid ion conductor is polycrystalline ${\mathrm{Li}}_{1+x+y}{\mathrm{Al}}_x$(${\mathrm{Ti}}_{2-y}{\mathrm{Ge}}_y$)${\mathrm{P}}_{3-z}{\mathrm{Si}}_z{\mathrm{O}}_{12}$ with the NASICON-type structure (O'Hara Inc.), which has high lithium ion conductivity of ${10}^{-4}$ S/cm or more at room temperature. The thin flake is ${\mathrm{FeSe}}_{0.5}{\mathrm{Te}}_{0.5}$, which is coated with Cr/Au electrodes for transport measurements. The back gate electrode is silver paste painted on the bottom surface of the solid ion conductor. (d) A gate-voltage dependence of the resistance of ${\mathrm{FeSe}}_{0.5}{\mathrm{Te}}_{0.5}$ thin flakes with thickness of 22 nm. The insert is the optical image of a ${\mathrm{FeSe}}_{0.5}{\mathrm{Te}}_{0.5}$ thin flake with the current and voltage terminals labeled.

Figure 2

(a) The typical in situ XRD patterns of the ${\mathrm{FeSe}}_{0.5}{\mathrm{Te}}_{0.5}$ thin fakes with thickness of 50 nm at various gating status. (b) The magnified view of the (001) diffraction peak.

Figure 3

(a) Gate voltage dependence of the resistance of a ${\mathrm{FeSe}}_{0.5}{\mathrm{Te}}_{0.5}$ thin flake with a thickness of 22 nm. (b) Hall number $n_H$ with various gate voltage applied, taken at $T=16$ K and 150 K. The low-temperature $n_H$ shows a sudden sign reversal around $V_g=5.22$ V. (c) The longitudinal resistance at various gating status. (d) Temperature dependence of Hall coefficient $R_H$, calculated from the linear fit of a $R_{xy}$(B) plot from $-9$ to 9 T. For the nonlinear $R_{xy}$(B) curves, $R_H$ was extracted from the slope of the high-field quasilinear part [15].

Figure 4

(a) The phase diagram of ${\mathrm{FeSe}}_{0.5}{\mathrm{Te}}_{0.5}$ thin flake as a function of gate voltage. (b) The phase diagram of Li-intercalated FeSe thin fake as a function of gate voltage, and the data was taken from Ref. [15].