Gate-controlled semimetal-topological insulator transition in an InAs/GaSb heterostructure

We report a gate-controlled transition of a semimetallic InAs/GaSb heterostructure to a topological insulator. The transition is induced by decreasing the degree of band inversion with front- and back-gate voltages. Temperature dependence of the longitudinal resistance peak shows the energy gap opening in the bulk region with increasing gate electric field. The suppression of bulk conduction and the transition to a topological insulator are confirmed by nonlocal resistance measurements using a dual lock-in technique, which allows us to rigorously compare the voltage distribution in the sample for different current paths without the influence of time-dependent resistance fluctuations.

Figure 1

Schematics of (a) band-edge profile of the sample used and (b) dispersion relations in a TI. (c),(d) Schematics illustrating the effects of gate electric field on the squared wave functions of electrons (red) and holes (blue) (upper panels) and band-edge profile (lower panels). The diagrams in (c) and (d) represent the flat-band condition and the case with the gate electric field increasing the electron-hole wave-function overlap, respectively. $E_{e0}$ and $E_{h0}$ indicate the energies of the electron and hole ground subbands, respectively. (e),(f) Schematic illustrations of the effects of gate electric field on the dispersion relation in the presence of valence-band anisotropy. (e) and (f) correspond to the situation in (c) and (d), respectively. The shaded regions indicate the energy range of the anticrossing gap for each $k$ direction.

Figure 2

(a) Schematic of sample structure. (b) Six-terminal device pattern and typical nonlocal resistance measurement setup using dual lock-in technique. The distance between adjacent contacts is $2\mu \mathrm{m}$. The side contacts on the opposite edges (2–6 and 3–5) are separated by $2\mu \mathrm{m}$.

Figure 3

(a) Longitudinal resistance ($R_{14,23}$) at different back-gate voltages ($V_{\text{BG}}$) as a function of front-gate voltage ($V_{\text{FG}}$). Inset: Magnified view of the the $R_{14,23}$ traces in the low-resistance regime. (b) Peak value of $R_{14,23}$ obtained from Gaussian fitting of the $R_{14,23}$ traces in (a), plotted as a function of $V_{\text{BG}}$. (c) Temperature dependence of $R_{14,23}$ peak at different $V_{\text{BG}}$. The data are plotted as a function of inverse temperature ($1/T$). The short dashed line is the Arrhenius fit to the data at $V_{\mathrm{BG}}=10$ V, with the slope corresponding to a gap of $0.2$ meV.

Figure 4

(a)–(d) Nonlocal resistances (a) $R_{16,34}$, (b) $R_{16,45}$, (c) $R_{21,34}$, and (d) $R_{21,45}$, measured at $V_{\text{BG}}=0$ and 10 V as a function of $V_{\text{FG}}$. (e),(f) Ratios of nonlocal resistances (voltages) measured with adjacent voltage-probe pairs. Results for different current paths are compared for $V_{\text{BG}}=$ (e) 10 and (f) 0 V. (g),(h) Equivalent circuits for TI and normal conductor, respectively.

Figure 5

Voltage ratios $V_{23}/V_{34}$ ($=R_{ij,23}/R_{ij,34}$) for current paths $I_{16}$ and $I_{65}$, measured at $V_{\mathrm{BG}}=$ (a) 0, (b) 4, (c) 6, and (d) 10 V.

Figure 6

Nonlocal resistance measurements at $V_{\mathrm{BG}}=10$ V for various contact geometries shown in the insets. In each panel, nonlocal resistance ratios for different current paths are plotted as a function of $V_{\mathrm{FG}}$ ($T=0.27$ K).