Origin of gate hysteresis in $p$-type Si-doped AlGaAs/GaAs heterostructures

Gate instability/hysteresis in modulation-doped $p$-type AlGaAs/GaAs heterostructures impedes the development of nanoscale hole devices, which are of interest for topics from quantum computing to novel spin physics. We present an extended study conducted using custom-grown, matched modulation-doped $n$-type and $p$-type heterostructures, with and without insulated gates, aimed at understanding the origin of the hysteresis. We show the hysteresis is not due to the inherent “leakiness” of gates on $p$-type heterostructures, as commonly believed. Instead, hysteresis arises from a combination of GaAs surface-state trapping and charge migration in the doping layer. Our results provide insights into the physics of Si acceptors in AlGaAs/GaAs heterostructures, including widely debated acceptor complexes such as Si-X. We propose methods for mitigating the gate hysteresis, including poisoning the modulation-doping layer with deep-trapping centers (e.g., by codoping with transition metal species) and replacing the Schottky gates with degenerately doped semiconductor gates to screen the conducting channel from GaAs surface states.

Figure 1

(a) Gate leakage current $I_g$ on a log-axis vs gate bias $V_g$ for a Schottky-gated modulation-doped $p$-type heterostructure. At positive $V_g$, $I_g$ remains less than 50 pA up to $V_g=+2$ V, sufficient to achieve pinch-off for all uninsulated gate devices studied. In an $n$-type heterostructure, gate leakage would normally occur at $V_g=+0.68$ V (indicated by the arrow) and is suppressed for negative $V_g$. (b) Channel current $I_d$ vs gate voltage $V_g$ at six different gate sweep rates for Device A. The horizontal arrows indicate the direction of travel around the hysteresis loop.

Figure 2

(a) Channel current $I_d$ and (b) gate leakage current $I_g$ vs gate voltage $V_g$ at three different gate sweep rates for Device B (20 nm Al${}_2$O${}_3$ layer on heterostructure 1-h). Horizontal arrows indicate sweep direction. In (b) the left/right axis and lower/upper data are for the up/down sweep, respectively. Once $I_g$ reaches 1 $\mu$A the gate voltage source implements current limiting, holding $V_g$ fixed. Hence, for $V_g\gtrsim +5.6$ V the data in (a) should be considered as $I_d$ vs time $t$ at fixed $V_g$, with each $0.2$ V minor tick in $V_g$ corresponding to 80, $40,$ and 20 s for sweep rates of $2.5$, 5, and 10 mV/s, respectively.

Figure 3

Channel current $I_d$ vs gate voltage $V_g$ for devices (a) without (Device D) and (b) with a 20 nm Al${}_2$O${}_3$ gate insulator (Device E) on heterostructure 1-e. The inset to (b) shows a close-up of the data in the main panel to highlight the hysteresis. The arrows indicate hysteresis loop direction. The purple dot-dashed lines are guides to the eye highlighting the low-bias nonlinearity.

Figure 4

Channel current $I_d$ vs gate voltage $V_g$ for (a) Device F on heterostructure 1-h and (b) Device G on heterostructure 1-h with sulfur passivation. The data in (a) are what we typically obtain with sulfur passivation, even with different treatments.[35] The data in (b) are a repeatable measurement, but, to date, a nonreproducible device. We are still working to establish reliable conditions that produce this outcome. The solid black and dashed blue traces were obtained at sweep rates of 10 and $2.5$ mV/s. The arrows indicate hysteresis loop direction.

Figure 5

[(a) and (b)] Channel current $I_d$ vs gate voltage $V_g$ for Device C on heterostructure 1-e without Al${}_2$O${}_3$ at $T=$ (a) 130 K and (b) 120 K. (c) A schematic illustrating an evident relationship between the hysteresis loop shape in hole (left) and electron devices (right), as discussed in the text. [(d)–(g)] $I$ vs $V_g$ for Device D on heterostructure 1-e with a 20 nm Al${}_2$O${}_3$ layer at $T=$ (d) 140 K, (e) 130 K, (f) 120 K, and (g) 110 K. In (a), (b), and (d)–(g) the solid black and dashed blue traces were obtained at sweep rates of 10 and $2.5$ mV/s. The arrows indicate hysteresis loop direction.

Figure 6

Channel current $I_d$ vs gate voltage $V_g$ for Device F on heterostructure 2-h without Al${}_2$O${}_3$ at $T=$ (a) $4.5$ K and (b) $3.0$ K, (c) $1.45$ K, (d) $1.14$ K, (e) 790 mK, (f) 500 mK, (g) 300 mK, and (h) 260 mK. (i) $I_d$ vs $V_g$ for Device H on the $\delta$-doped heterostructure 3-h without Al${}_2$O${}_3$/passivation at $T=4$ K. The solid black and dashed blue traces were obtained at sweep rates of 10 and $2.5$ mV/s. The arrows indicate hysteresis loop direction.

Figure 7

(a) Optical micrograph of a completed device with 10 ohmic contacts (3 at each end and 4 near the middle) and a single top-gate covering the midsection of the Hall bar with interconnects at top and bottom. The remaining four metal gates were not used. (b) Nomarski phase-contrast optical micrograph showing four etched penetrations (off-white) in the 20 nm Al${}_2$O${}_3$ layer (pink) obtained using a buffered HF etch. These correspond to the four central ohmic contacts in (a). (c) Scanning electron micrograph of the etch penetration (dark) in the Al${}_2$O${}_3$ layer (light) for the ohmic contact at the far right of the Hall bar in (a). (b) and (c) were obtained after the buffered HF etch and before ohmic metallization.

Figure 8

Gate leakage current $I_g$ on a linear axis vs gate bias $V_g$ for a Schottky-gated modulation-doped $p$-type heterostructure. The data match those shown in Fig. 1a. At positive $V_g$, $I_g$ remains less than 50 pA to $V_g=+2$ V, sufficient to achieve pinch-off for all uninsulated gate devices studied. In an $n$-type heterostructure, gate leakage would normally occur at $V_g=+0.68$ V (indicated by the arrow) and is suppressed for negative $V_g$.

Figure 9

(a) The hysteresis loop vertical extent $I_{\mathrm{down}}-I_{\mathrm{up}}$ and (b) the numerical transconductance $d{I}_d/d{V}_g$ for the upsweeps vs gate voltage $V_g$. The traces in (b) are sequentially offset vertically by $+0.05$ with increasing sweep rate for clarity.

Figure 10

Channel current $I_d$ vs gate voltage $V_g$ for 22 hysteresis loop sweeps of Device B2. The first sweep is show in blue, and the second to twenty-second sweeps evolve continuously in color from green to magenta. The sweep rate in each case is 5 mV/s. The points of discontinuity at high $V_g$ are where gate voltage current limiting comes on/off for the up/downsweep.

Figure 11

(a) Channel current $I_d$ and (b) gate leakage current $I_g$ vs gate voltage $V_g$ at two different gate sweep rates for a Device C featuring a 140 nm polyimide layer on 2-h. The horizontal arrows indicate the direction of travel around the hysteresis loop. In (b) the left/right axis and lower/upper set of data are for the sweep to/from positive $V_g$, respectively. Note that once $I_g$ reaches 50 nA the gate voltage source implements current limiting by holding $V_g$ fixed. Hence, for $V_g\gtrsim +3.2$ V the data in (a) should be considered as $I_d$ vs time $t$ at fixed $V_g$. To aid in converting the data at $V_g\gtrsim +3.2$ V into time, each 0.2 V minor tick in the figure corresponds to 40 and 20 s for sweep rates of 5 and 10 mV/s, respectively.