Functional Basis for Efficient Physical Layer Classical Control in Quantum Processors

The rapid progress seen in the development of quantum-coherent devices for information processing has motivated serious consideration of quantum computer architecture and organization. One topic which remains open for investigation and optimization relates to the design of the classical-quantum interface, where control operations on individual qubits are applied according to higher-level algorithms; accommodating competing demands on performance and scalability remains a major outstanding challenge. In this work, we present a resource-efficient, scalable framework for the implementation of embedded physical layer classical controllers for quantum-information systems. Design drivers and key functionalities are introduced, leading to the selection of Walsh functions as an effective functional basis for both programing and controller hardware implementation. This approach leverages the simplicity of real-time Walsh-function generation in classical digital hardware, and the fact that a wide variety of physical layer controls, such as dynamic error suppression, are known to fall within the Walsh family. We experimentally implement a real-time field-programmable-gate-array-based Walsh controller producing Walsh timing signals and Walsh-synthesized analog waveforms appropriate for critical tasks in error-resistant quantum control and noise characterization. These demonstrations represent the first step towards a unified framework for the realization of physical layer controls compatible with large-scale quantum-information processing.

Figure 1

(a) A finite set of the Walsh functions appearing in Paley ordering with normalized total durations. Walsh functions highlighted in bold correspond to the Thue-Morse subset, possessing Paley-ordered indices with the highest binary Hamming weight. (b) Example trace showing how a Paley-order Walsh function with index 12, ${\mathsf{W}}_{12}$ yields the pulse locations for a ${\mathrm{WDD}}_{12}$ sequence via the location of digital transitions. Vertical lines schematically indicate control-pulse locations, normalized to the total time, $T$. (c) Sample Walsh-synthesized-filter waveforms providing first- and second-order noise filtering. Shown are a red trace composed of the Walsh functions highlighted in red above, as well as a blue trace composed of the Walsh functions highlighted in both red and blue. A red dashed line indicates that arbitrary shapes for individual pulse segments can be accommodated with the Walsh waveform defining the overall amplitudes of each segment [42].

Figure 2

Schematic of a high-efficiency real-time Walsh-function generator implemented in a FPGA. Square-wave Rademacher functions are summed with the binary digits of the desired Walsh function in Paley ordering via a cascade of lookup tables (LUTs), each composed of an xor gate and a multiplexer. Timing of the Rademacher functions is set by the clk-expand input such that the base time period of the Walsh function is a fixed multiple of the clock period. The enable input begins the signal generation via an external hardware trigger. (Lower panel) Real-time oscilloscope data capture of Rademacher functions of various orders, with the period increasing by a factor of 2 with each increase in the Rademacher order. The two light-blue Rademacher functions (${\mathsf{R}}_2$ and ${\mathsf{R}}_3$) undergo modular addition via the Walsh generator to form the output Walsh function with Paley order 12 ($12=2^3+2^2$, or $12\to 1100$, $b_2=b_3\ne 0$), shown in dark blue at the bottom of the figure. Additional circuitry has been constructed to route Rademacher functions to digital output pins for this diagnostic measurement. In this demonstration, we employ a Xilinx Zynq 7010 as part of a dual-core ARM Coretex $\mathrm{A}9+\mathrm{FPGA}$ system-on-a-chip packaged by Red Pitaya.

Figure 3

Schematic of a high-efficiency real-time Walsh-based controller implemented in a FPGA. (a) Key subsystems used to fulfill the summary requirements listed in the text. Inputs to the timing sequencer include “start,” which triggers the output, “reset,” which resets the state of the system, “repeat,” which determines $R$, the number of sequence repeats, “$t_1$,” which sets the clock expansion on the signal “clk” for the primary Walsh timing signal, and “order,” which selects the Paley-ordered Walsh function to define the timing signal. The Walsh modulation generator takes as input the “trigger” signal output by the timing sequencer as well as another clock and clock-expansion parameter. The Walsh filter synthesizer takes input Walsh sequences, denoted $W^{*}$ as well as “weights,” which define the analog Walsh-synthesis coefficients, “mode,” which selects the modulation protocol, and a clock. All clock signals are generated by a phase-lock loop. We employ two clocks with equivalent frequencies but differing by a $\pi$ phase shift for the timing sequencer and the two subsequent modules, respectively; this approach results in a half-clock-cycle delay as observed in (c). (b) Representative sample outputs of the relevant main subsystems using our FPGA implementation and captured using an oscilloscope. The red vertical dotted lines indicate trigger locations associated with Walsh timing: here, ${\overline{\mathsf{W}}}_3$ repeated twice. In this example, I-DAC corresponds to an AM-only Walsh noise-filtering protocol highlighted in (c). The modulation waveform for each pulse provides a first-order Walsh-amplitude-modulated filter via a weighted sum of ${\mathsf{W}}_0$ and ${\mathsf{W}}_3$. The first six Walsh functions generated by the Walsh modulation generator on a trigger from the timing sequencer are shown. Again, in order to access signals not typically routed directly to FPGA outputs (e.g., the synthesized Walsh functions), additional FPGA circuitry is implemented for diagnostics only.

Figure 4

Schematic of Walsh-based system-identification (SID) module implemented in a FPGA. (a) Here, the red shaded box indicates a protocol performed either at the qubit level or, as here, in simulation, returning fidelities $P_k$ from measurements $M$ and feeding them to Walsh-estimation modules (b). The input parameter $D$ is responsible for scaling the arcsin function, taking the value $D=\gamma T$. The output of the weight-summation module is the reconstructed signal $\widehat{b}(t)$ for the magnetic field, represented digitally and here used to program a DAC for signal monitoring. (b) Detailed schematic of weight estimation. The 13-bit binary presentation of fidelity ($P_k$) doubles its value by using a shift-left 1-bit register and then subtracts to 14-bit binary presentation of 1 to derive $\arcsin (\gamma T{X}_k)$, as shown in Eq. (c4). The arcsin LUT is a $2^{14}$-element lookup table which returns $T{X}_k$. A divider is used to scale the output of arcsin LUT with divisor $T$ and output the final result, Walsh weights $X_k$. The selected value of the bit depth for the arcsin function is determined by the specific hardware implementation employed here. (c),(d) Analog waveforms output from the DAC overlaid with an applied noise signal given numerically calculated values for $P_k$, using 16 or 32 Walsh functions (and, hence, individual fidelity measurements).

Figure 5

Schematic of the Walsh filter synthesizer employed in the Walsh controller. The bit widths of relevant signals are indicated. AM, $\mathrm{\Phi }\mathrm{M}$, or QAM modulation is selected by the mode input, activating the relevant subunits. We distinguish the outputs of the AM and $\mathrm{\Phi }\mathrm{M}$ arbitrators using the superscripts on ${\mathrm{\Sigma }}_W^{(1,2)}$. The $\mathrm{\Phi }\mathrm{M}$ subsystem relies on built-in DDS blocks in the FPGA to directly rotate outputs to the appropriate basis. The QAM arbitrator takes 14-bit inputs and uses only the seven most significant bits prior to multiplication. This DDS is enabled by the “data valid” input generated by the Walsh modulation generator (Fig. 3). Relationships of outputs under various modulation protocols, indicated by the mode input, are indicated at the bottom of the panel. (b) Within the AM and $\mathrm{\Phi }\mathrm{M}$ modules, we construct the sum-weights submodule (the blue dashed box). Red boxes are highlighted in the inset and demonstrate the bitwise selection of $\pm X_k$, depending on the value of ${\mathsf{W}}_k^{(2)}$.

Figure 6

Waveforms illustrating timing and latency distribution for generating output signals via the FPGA modules. Clock signals (the first two waveforms) are generated by a phase-lock loop to minimize clock skew. These generated clocks take one of two forms: clk (used for the timing sequencer) or the complement form $\overline{\mathrm{clk}}$ (used for the Walsh modulation generator and the Walsh filter synthesizer). Latency distribution of internal signals start, trigger, and $W^{*}$ and output signal $I$ are also indicated in terms of the number of clock cycles (see Fig. 3).