Field-Effect Transistors with Submicrometer Gate Lengths Fabricated from ${\mathrm{LaAlO}}_3\text{−}{\mathrm{SrTiO}}_3$-Based Heterostructures

The possible existence of short-channel effects in oxide field-effect transistors is investigated by exploring field-effect transistors with various gate lengths fabricated from ${\mathrm{LaAlO}}_3\text{−}{\mathrm{SrTiO}}_3$ heterostructures. The studies reveal the existence of channel-length modulation and drain-induced barrier lowering for gate lengths below $1\mu \mathrm{m}$, with a characteristic behavior comparable to semiconducting devices. With the fabrication of field-effect transistors with gate lengths as small as 60 nm, the results demonstrate the possibility to fabricate by electron-beam lithography functional devices based on complex oxides with characteristic lengths of several tens of nanometers.

Figure 1

Sketch of a cross section of a FET.

Figure 2

HAADF STEM cross-sectional images at (a) lower magnification and (b) high magnification of the ${\mathrm{SrTiO}}_3$ substrate, the ${\mathrm{LaAlO}}_3$ and ${\mathrm{BaTiO}}_3$ layers, and the Au capping layer, where a misfit dislocation in ${\mathrm{BaTiO}}_3$ is indicated in (b). (c) ADF STEM image (left) and the respective background-subtracted unfiltered EELS elemental maps (Ba, green; La, red; Sr, blue; Ti, yellow) of the region underneath the gate electrode. The right image is a RGB overlay of the Ba, La, and Sr maps. The scale bar in the ADF image in (c) applies also for the EELS elemental maps.

Figure 3

(a) Photograph of a $10\times 10{\mathrm{mm}}^2$-sized sample patterned by electron-beam lithography. It comprises several hundred FETs and further test devices. The gate lengths as designed vary from 50 nm to $5\mu \mathrm{m}$. (b) False-colored scanning electron microscopy image of a FET with 60-nm gate length and a source-drain distance of 600 nm. The 2DEL forms a rectangular region connecting the source and drain electrodes and is surrounded by insulating amorphous ${\mathrm{LaAlO}}_3$. For all FETs on this chip, the aspect ratio of the gated area is the same ($W_G/L_G=15$).

Figure 4

Drain-source transport characteristics of FETs representing three gate-length regimes: (a) long channel lengths ($L_G=5\mu \mathrm{m}$), (b) intermediate channel lengths ($L_G=500\mathrm{nm}$) with arising short-channel effects, and (c) short-channel-effect-dominated length scales ($L_G=60\mathrm{nm}$). The data are taken in the dark and at room temperature.

Figure 5

Transfer characteristics of the FETs for the three different gate-length regimes shown in Fig. 4. With decreasing gate length, the threshold voltage shifts to lower values and is increasingly dependent on the source-drain voltage. Additionally, the on-off ratio and subthreshold slope decrease. The dashed lines show the absolute value of the gate current. The data are taken in the dark and at room temperature.