Design and Cryogenic Operation of a Hybrid Quantum-CMOS Circuit

Silicon-on-insulator nanowire transistors of very small dimensions exhibit electrostatic or quantum effects like Coulomb blockade or single-dopant transport at low temperature. The same process also yields excellent field-effect transistors (FETs) for larger dimensions, allowing us to design integrated circuits. Using the same process, we cointegrate a FET-based ring oscillator circuit operating at cryogenic temperature which generates a radio-frequency (rf) signal on the gate of a nanoscale device showing Coulomb oscillations. We observe rectification of the rf signal, in good agreement with modeling.

Figure 1

Schematics of the whole circuit designed and fabricated on 300-mm SOI wafers. The nanowire showing Coulomb blockade below 10 K is on the right. The CMOS circuit driving the gates is made of several subcircuits. A voltage-controlled oscillator (VCO) monitored through a frequency divider feeds a clock generator also based on ring oscillators. This generator delivers two delayed and phase-shifted rf signals, rf 1 and rf 2, which are further attenuated by capacitive dividers and added to external dc biases. The voltage supply $V_{DD}$ referenced to ground GND is not shown.

Figure 2

(a) Schematics of the VCO using a nand gate at the input as a switch and 20 stages of inverters. (b) Detail of a single inverter stage made of a conventional inverter cell on top (associating $N$- and $P$-type transistors) and a NMOS transistor at the bottom.

Figure 3

(a) View of the silicon chip with 12 aluminum contact pads for the whole circuit. The bias resistors implemented at the active area level are not visible in this picture of a finished device after encapsulation. The capacitors are the square arrays made between copper layers of the back-end process. (b) Detailed view of the CMOS transistors and the nanowire with the gate level in green, active area in blue, and metallic vias and lines in red. The top part is the VCO (approximately 130 transistors) and nonoverlapping clock generator (approximately 100 transistors), while the bottom part is the frequency divider (approximately 400 transistors). Both are made with the same wide transistors ($W=1\mu \mathrm{m}$) featuring 60-nm-long gates, as depicted in (c). The connections between the group of circuits are not shown for clarity. (d) Detailed view of the single-electron device having a 25-nm-wide channel and a 40-nm-long gate.

Figure 4

Output frequency of the voltage-controlled oscillator measured at 300, 77, and 4.2 K after correction by the frequency divider (division by a factor of 65 536). The maximum output frequencies are 1.36 GHz at 300 K, 1.08 GHz at 77 K, and 1.06 GHz at 4.2 K.

Figure 5

(a) Frequency response of the VCO at 1.1 K versus back-gate voltage $V_{\mathrm{BG}}$. An optimal working point is found around $-8\mathrm{V}$. (b) Frequency response versus VCO at different $V_{\mathrm{BG}}$.

Figure 6

(a) Coulomb blockade oscillations measured at 1.1 K with a lock-in amplifier with an ac signal of $100\mu \mathrm{V}$ at 77 Hz. (b) dc current measured at 1.1 K when $V_{\mathrm{DS}}^{\mathrm{dc}}=0$ but CMOS circuit switched on, with amplitude $500\mu \mathrm{V}$ at 412 MHz. (c) dc current calculated with the rectification model. We find good agreement with the measured current shown in (b). The current follows the derivative of the transconductance, i.e., the second derivative of the conductance.