Cryogenic Control Architecture for Large-Scale Quantum Computing

Solid-state qubits have recently advanced to the level that enables them, in principle, to be scaled up into fault-tolerant quantum computers. As these physical qubits continue to advance, meeting the challenge of realizing a quantum machine will also require the development of new supporting devices and control architectures with complexity far beyond the systems used in today’s few-qubit experiments. Here, we report a microarchitecture for controlling and reading out qubits during the execution of a quantum algorithm such as an error-correcting code. We demonstrate the basic principles of this architecture using a cryogenic switch matrix implemented via high-electron-mobility transistors and a new kind of semiconductor device based on gate-switchable capacitance. The switch matrix is used to route microwave waveforms to qubits under the control of a field-programmable gate array, also operating at cryogenic temperatures. Taken together, these results suggest a viable approach for controlling large-scale quantum systems using semiconductor technology.

Figure 1

PL-AL architecture that separates prime analog waveforms used to manipulate qubits from the addressing data used to select qubits. (a) An example subsection of a quantum algorithm shown using quantum-circuit notation. The highlighted clock cycles include single-qubit rotations (yellow), a two-qubit gate (green), and readout operation (red). Note that multiple operations are intended in a given clock cycle such that the required analog waveform for control or readout can be connected in parallel to any qubit. (b) Prime lines corresponding to a universal gate set are routed to qubits via a switch matrix controlled by the address lines. Colored paths correspond to the highlighted clock cycles in (a). Vertical dashed lines indicate the clocking of the analog prime waveforms which occurs at a rate that is 10–100 times slower than the clocking of the address bus. The clock rate of the address bus will depend on its width and qubit coherence times.

Figure 2

Schematic of a control microarchitecture that distributes subsystems across the various temperature stages of a dilution refrigerator, depending on the available cooling power (image is of a Leiden Cryogenics CF450). A millikelvin switch matrix on the same chip as the qubit device or close to it steers a small number of control pulses to qubits using addressing information from cryogenic logic at 4 K. The matrix will incorporate a level of digital decoding to enable switch addresses to be transmitted on a relatively small number of serial lines.The cryogenic logic also interfaces with multiplexed readout and digital-to-analog converters (DAC). The 4-K stage typically has a cooling power of approximately 1 W, with the 20-mK stage having less than $10\mu \mathrm{W}$.

Figure 3

Characterization of a HEMT switch as a building block for the PL-AL architecture. (a) Microscope photograph of the device fabricated on $\mathrm{GaAs}/{\mathrm{Al}}_{0.3}{\mathrm{Ga}}_{0.7}\mathrm{As}$ heterostructure. (b) Schematic cross section showing the coplanar line diverted through the 2DEG. A negative voltage ($-300\mathrm{mV}$) on the top gate increases the impedance of the switch, reflecting the input signal. (c) Transmission as a function of frequency for the on (blue) and off (red) state. (d) Example of time-domain response. When the gate voltage (green) is zero, the 120-MHz sine wave provided at the switch input is propagated to the output (blue), and not otherwise. (e) Modulating a carrier signal through the 2DEG with a sinusoidal gate voltage creates sidebands. The amplitude of the sidebands as a function of frequency indicates a (1–2)-ns switching time.

Figure 4

A switch design that produces an impedance mismatch by depleting the transmission-line ground plane. Shown is an image (a) and cross sections (b) of the device. The input is a coplanar line [(i)] which transitions to a microstrip using the 2DEG as the ground plane [(ii),(iii)]. The ground plane is tapered so that it lies beneath the signal track [(iv),(v)]. When a negative voltage is applied to the signal track, the ground plane is depleted [(v)], and the impedance mismatch reflects the input signal. (c) Transmission through the switch in the on (blue) and off (red) states. (d) Frequency response of capacitors formed using surface gates and 2DEG as a parallel plate (inset).

Figure 5

Small-scale two-input–two-output switch matrix based on HEMT switches, with on-chip bias tees for quantum-dot operation. Device image is shown in (a) with associated circuit diagram in (b). (c) Transmission measurement with path A (blue) in the on state and path B (red) in the off state. (d) Voltage output with a 1-GHz input tone where path A is in the on state and path B is (i) off, and (ii) half on. (e) An example of IQ modulation implemented by feeding the input ports of the $2:2$ matrix with signals that have a 90° phase offset. Arbitrary amplitude and phase is produced at the output (data shown in figure) by selecting the appropriate $V_{i,j}$ (see main text). (f) Example voltage output for one of the constant amplitude quarter circles in (e).

Figure 6

Simple implementation of the microarchitecture introduced in Fig. 2. (a) Experimental setup for measuring a double quantum dot using a cryogenic FPGA to steer pulses via a millikelvin switch matrix. Charge-state readout is performed using a rf quantum point contact (QPC). (b) Switch matrix output showing a 100-kHz square wave directed to plunger gates of the quantum dot. (c) Micrograph of the quantum-dot device. The shaded gates labeled LP and RP are connected to the switch matrix output. (d)–(g) Charge sensing of the double quantum dot in the few-electron regime, with electron occupancy indicated by the labels (m,n). The color axis is the derivative of the sensing signal $V_{\mathrm{r}\mathrm{f}}$ with respect to $V_R$. When the FPGA-controlled switch matrix blocks waveforms (d), a standard double-dot stability diagram is detected. When the square wave is directed to either LP (e), RP (f), or both (g), copies of the stability diagram appear (see text). These measurements demonstrate that the double-dot potential can be controlled autonomously by the switch matrix and cold FPGA.