Promising Properties of a Sub-5-nm Monolayer ${\mathrm{Mo}\mathrm{Si}}_2{\mathrm{N}}_4$ Transistor

Two-dimensional (2D) semiconductors have attracted tremendous interest as natural passivation and atomically thin channels could facilitate continued transistor scaling. However, air-stable 2D semiconductors with high performance are quite elusive. Recently, an extremely-air-stable ${\mathrm{Mo}\mathrm{Si}}_2{\mathrm{N}}_4$ monolayer was successfully fabricated [Hong et al., Science 369, 670 (2020)]. To further reveal its potential application in sub-5-nm metal-oxide-semiconductor field-effect transistors (MOSFETs), there is an urgent need to develop integrated circuits. Here, we report first-principles quantum-transport simulations on the performance limits of n- and p-type sub-5-nm monolayer (ML) ${\mathrm{Mo}\mathrm{Si}}_2{\mathrm{N}}_4$ MOSFETs. We find that the on-state current in the ${\mathrm{Mo}\mathrm{Si}}_2{\mathrm{N}}_4$ MOSFETs can be effectively manipulated by the length of gate and underlap, as well as the doping concentration. Very strikingly, we also find that for the n-type devices the optimized on-state currents can reach up to 1390 and 1025 µA/µm for high-performance and low-power (LP) applications, respectively, both of which satisfy the International Technology Roadmap for Semiconductors (ITRS) requirements. The optimized on-state current can meet the LP application (348 µA/µm) for p-type devices. Finally, we find that the ${\mathrm{Mo}\mathrm{Si}}_2{\mathrm{N}}_4$ MOSFETs have an ultralow subthreshold swing and power-delay product, which have the potential to realize high-speed and low-power consumption devices. Our results show that ${\mathrm{Mo}\mathrm{Si}}_2{\mathrm{N}}_4$ is an ideal 2D channel material for future competitive ultrascaled devices.

Figure 1

(a) Top view and side view of ML ${\mathrm{Mo}\mathrm{Si}}_2{\mathrm{N}}_4$; dashed lines represent the primitive unit cell of ML ${\mathrm{Mo}\mathrm{Si}}_2{\mathrm{N}}_4$. Blue, purple, and white balls represent silicon, molybdenum, and nitrogen atoms, respectively. (b) Band-decomposed charge-density distributions corresponding to valence-band maximum (VBM) and conduction-band minimum (CBM) of ML ${\mathrm{Mo}\mathrm{Si}}_2{\mathrm{N}}_4$. Isovalue is 0.02 e/bohr³. (c) Electronic band structure of monolayer ${\mathrm{Mo}\mathrm{Si}}_2{\mathrm{N}}_4$. Different orbitals of $\mathrm{Mo}$ are mapped with different colors: $\mathrm{Mo}$ d_xy orbital, blue; $\mathrm{Mo}$ d_yz orbital, green; $\mathrm{Mo}$ d_xz orbital, red; $\mathrm{Mo}$ $d_{z^2}$ orbital, magenta; $\mathrm{Mo}$ $d_{x^2-y^2}$ orbital, purple; $\mathrm{Mo}$ s orbital, orange. (d) Transmission eigenstates at K point (1/3,1/3) and E = 0.32 eV under on-state conditions (V_g = 0 V). Isovalue is 0.2 arb. units.

Figure 2

(a) Schematic diagram of the DG ML ${\mathrm{Mo}\mathrm{Si}}_2{\mathrm{N}}_4$ MOSFETs. (b)–(g) I-V_g characteristics of n- and p-type FETs with different gate lengths and L_UL for V_b = 0.64 V.

Figure 3

(a)–(d) On-state current as a function of gate length for n- (a, c) and p-type (b, d) FETs with different L_UL for the HP (a, b) and LP (c, d) applications, respectively. Black dashed lines represent the ITRS HP and LP requirements.

Figure 4

Spatially resolved LDOS and transmission spectra for n-type FETs in the off (a)–(d) and on states (e)–(h) with 1-nm gate length. (a), (b), (c) represent the LDOS of off state with underlap length of 0 nm, 2 nm, 4 nm, respectively. (e), (f), (g) are the on-state LDOS with underlap length of 0 nm, 2 nm, 4 nm, respectively. (d) and (h) correspond to the transmission spectra of off and on states with different underlap length, respectively. Transmission spectra near the CBM of ${\mathrm{Mo}\mathrm{Si}}_2{\mathrm{N}}_4$ are shown in the inset in (h). µ_S and µ_D are the electrochemical potentials of the source and drain, respectively.

Figure 5

SS as a function of gate length for (a) n- and (b) p-type FETs with different L_UL. Black dashed lines indicate the Boltzmann limit of 60 mV/dec for SS at room temperature.

Figure 6

Intrinsic delay time (τ) (a),(b) and PDP (c),(d) as a function of gate length for n- and p-type FETs with different L_UL. Black dashed lines are the ITRS HP and LP requirements for τ and PDP, respectively.