Electrical Properties of Selective-Area-Grown Superconductor-Semiconductor Hybrid Structures on Silicon

We present a superconductor-semiconductor materials system that is both scalable and monolithically integrated on a silicon substrate. It uses selective-area growth of $\mathrm{Al}$-$\mathrm{In}\mathrm{As}$ hybrid structures on a planar III-V buffer layer, grown directly on a high-resistivity silicon substrate. We characterize the electrical properties of this materials system at millikelvin temperatures and observe a high average field-effect mobility of $\mu \approx 3200{\mathrm{cm}}^2\mathrm{/Vs}$ for the $\mathrm{In}\mathrm{As}$ channel and a hard induced superconducting gap. Josephson junctions exhibit a high interface transmission, $\mathcal{T}\approx 0.75$, a gate-voltage-tunable switching current with a product of critical current and normal state resistance, $I_C{R}_N\approx 83\mu \mathrm{V}$, and signatures of multiple Andreev reflections. These results pave the way for scalable and high-coherence gate-voltage-tunable transmon devices and other superconductor-semiconductor hybrids fabricated directly on silicon.

Figure 1

(a) A schematic of the material stack. The $\mathrm{In}\mathrm{As}$ quantum well (green) is proximitized by the superconducting $\mathrm{Al}$ (blue). (b) A false-colored scanning transmission electron micrograph of the material stack.

Figure 2

False-colored scanning electron micrographs of the device types measured in this work. The false colors indicate nanowire segments with $\mathrm{Al}$ removed (green) and segments covered with $\mathrm{Al}$ (blue). (a) The field-effect transistor (FET) device. (b) The combined N-I-S′ spectroscopy and S-Sm-S JJ device. The middle segment serves as ground for both N-I-S′ spectroscopy and junction measurements. On some wafers, poor selectivity during SAG leads to material deposition on the oxide mask [19], which is visible as small grains in both SEMs.

Figure 3

The differential conductance $G$ as a function of the gate voltage $V_{G1}$ of an up and down sweep of a single nanowire (blue) and up sweeps of two nanowires with a different orientation and similar width $w$. A fit to the linear region of the green pinch-off curve is shown and used to determine the field-effect mobility according to Eq. (1). Upper left inset: a schematic showing the orientation of the nanowires relative to the major flat of the $\mathrm{Si}$ substrate. Lower right inset: the conductance in the fully open regime as a function of $w$. Solid lines indicate fits of the form $G_{\max }=g\mathrm{\prime }w$, where $g\mathrm{\prime }$ is the conductance per unit width of the nanowires in the fully opened regime. All the data shown in this figure are corrected for a line resistance $R_{\mathrm{line}}=4.9\mathrm{k}\mathrm{\Omega }$.

Figure 4

(a) The differential conductance $dI/dV$ of nanowire A as a function of the gate voltage $V_{G2}$ and the source-drain voltage $V_{SD}$. (b) Vertical cuts in the tunneling regime (red) and in the open regime (blue) at the positions indicated by the colored rectangles in (a). The induced superconducting gap ${\mathrm{\Delta }}^{\ast }\approx 190\mu \mathrm{eV}$ is estimated from the peak-to-peak distance in the tunneling regime. (c) The averaged differential conductance at zero source-drain voltage $G_S$ versus the averaged differential conductance at finite source-drain voltage $G_N$ ($V_{SD2})=-0.53\mathrm{mV}$ based on the data set in Fig. S4a of the Supplemental Material [20]. The green line is the theoretically predicted conductance in an Andreev-enhanced QPC with no fitting parameters [Eq. (2)].

Figure 5

(a) The measured voltage drop across the JJ $V_{SD3}$ as a function of the applied current $I_{SD3}$ for $V_{G3}=1.5\mathrm{V}$ for nanowire C. The normal-state resistance $R_N$ and excess current $I_{\mathrm{exc}}$ are extracted by fitting to the normal state for voltages $V_{SD3}>2\mathrm{\Delta }/e$. From these measurements, we estimate $\mathrm{\Delta }\approx 200\mu \mathrm{eV}$ at $T=20\mathrm{mK}$. The inset shows the region around the superconducting plateau with an up and down sweep of the current bias. The positions of the switching current $I_{\mathrm{sw}}$ and the retrapping current $I_R$ are indicated by arrows. (b) The differential resistance $dV/dI$ as a function of the applied current $I_{SD3}$ and the gate voltage $V_{G3}$ at $T=20\mathrm{mK}$ for nanowire C. (c) The extracted values for $R_N$, $I_{\mathrm{exc}}$, $I_{\mathrm{sw}}$, and $I_R$, extracted for nanowire B from the data set shown in the Supplemental Material [20]. (d) The $I_{\mathrm{sw}}{R}_N$ product and the excess current $I_{\mathrm{exc}}$ multiplied by the ratio $e{R}_N/\mathrm{\Delta }$ for $\mathrm{\Delta }=200\mu \mathrm{eV}$ extracted from (c). (e) $e{I}_{\mathrm{exc}}{R}_N/\mathrm{\Delta }$ and $e{I}_{\mathrm{sw}}{R}_N/\mathrm{\Delta }$ as a function of the temperature $T$, calculated from data shown in Fig. S5 of the Supplemental Material [20]. The solid lines indicate the temperature dependence expected from BCS interpolation [Eq. (3)].

Figure 6

(a) The averaged differential resistance $dV/dI$ for $1.3\mathrm{V}<V_{G2}<1.5\mathrm{V}$. The visible MAR peak positions for orders $m=1$–5 are indicated by vertical dotted lines for nanowire C. (b) The fit to the MAR peak position yielding a superconducting gap $\mathrm{\Delta }\approx 200\mu \mathrm{eV}$. (c) $dV/dI$ as a function of the measured voltage drop across the JJ $V_{SD}$ and sample temperature $T$. (d) The MAR peaks for $m=2,3$ as a function of the temperature. The red lines indicate the expected MAR peak positions based on $\mathrm{\Delta }(T)$ [Eq. (3)] with $\mathrm{\Delta }=200\mu \mathrm{eV}$.